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© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.comAN-6076
Design and Application Guide of Bootstrap Circuit for
High-Voltage Gate-Drive IC
Rev. 1.4 • 12/18/14
www.fairchildsemi.com
1. Introduction
The purpose of this paper is to demonstrate a systematic
approach to design high-performance bootstrap gate drivecircuits for high-frequency, high-power, and high-efficiencyswitching applications usin g a power MOSFET and IGBT.
It should be of interest to power electronics engineers at alllevels of experience. In the mo st of switching applications,
efficiency focuses on switching losses that are mainly depen-dent on switching speed. Theref ore, the switching character-
istics are very important in most of the high-power switchingapplications presented in this paper. One of the most widelyused methods to supply power to the high-side gate drive cir-cuitry of the high-voltage gate-drive IC is the bootstrappower supply. This bootstrap power supply technique has theadvantage of being simple and low cost. However, it hassome limitations, on time of duty-cycle is limited by therequirement to refresh the charge in the bootstrap capacitorand serious problems occur when the negative voltage is pre-sented at the source of the switching device. The most popu-lar bootstrap circuit solutions are analyzed; including the
effects of parasitic elements , the bootstrap resistor, and
capacitor; on the charge of the floating supply application.
2. High-Speed Gate-Driver Circuitry
2.1 Bootstrap Gate-Drive Technique
The focus of this topic is the bootstrap gate-drive circuitrequirements of the power MOSFET and IGBT in variousswitching-mode power-conver sion applications. Where
input voltage levels prohibit the use of direct-gate drive cir-cuits for high-side N-channel power MOSFET or IGBT, theprinciple of bootstrap gate-drive technique can be consid-ered. This method is utilized as a gate drive and accompany-
ing bias circuit, both refere nced to the source of the main
switching device. Both the driver and bias circuit swingbetween the two input voltage rails together with the sourceof the device. However, the driver and its floating bias canbe implemented by low-voltage circuit elements since theinput voltage is never applied across their components. Thedriver and the ground referenced control signal are linked bya level shift circuit that must tolerate the high-voltage differ-ence and considerable capacitiv e switching currents between
the floating high-side and gr ound-referenced low-side cir-
cuits. The high-voltage gate-d rive ICs are differentiated byunique level-shift design. To maintain high efficiency and
manageable power dissipation, the level-shifters should notdraw any current during the on-time of the main switch.
A widely used technique for these applications is called
pulsed latch level translators, shown in Figure 1.
Figure 1. Level-Shifter in High-Side Drive IC
2.2 Bootstrap Drive Circuit Operation
The bootstrap circuit is useful in a high-voltage gate driverand operates as follows. When the V
S goes below the IC
supply voltage VDD or is pulled down to ground (the low-
side switch is turned on and the high-side switch is turnedoff), the bootstrap capacitor, C
BOOT , charges through the
bootstrap resistor, RBOOT , and bootstrap diode, DBOOT , from
the VDD power supply, as shown in Figure 2. This is pro-
vided by VBS when VS is pulled to a higher voltage by the
high-side switch, the VBS supply floats and the bootstrap
diode reverses bias and blocks the rail voltage (the low-sideswitch is turned off and high-side switch is turned on) fromthe IC supply voltage, V
DD.
Figure 2. Bootstrap Power Supply CircuitUVLO
PULSE GENERATOR
RR
S QVB
NOISE
CANCELLER
Shoot-through current
compensated gate driverHO
VSIN
COMDC SUPPLY
LOADVDD Q1
Q2RG2RG1DBOOT
CBOOTILOADRBOOT
VDD
LOHOVB
VSBootstrap charge current path
Bootstrap discharge current path

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 22.3 Drawback of Bootstrap Circuitry
The bootstrap circuit has the advantage of being simple and
low cost, but has some limitations.
Duty-cycle and on time is limited by the requirement to
refresh the charge in th e bootstrap capacitor, CBOOT .
The biggest difficulty with this circuit is that the negative
voltage present at the source of the switching device duringturn-off causes load current to suddenly flow in the low-side
freewheeling diode, as shown in Figure 3.
This negative voltage can be trouble for the gate driver’s out-
put stage because it directly affects the source V
S pin of the
driver or PWM control IC and might pull some of the inter-nal circuitry significantly below ground, as shown in Figure4. The other problem caused by the negative voltage tran-sient is the possibility to develop an over-voltage conditionacross the bootstrap capacitor.
The bootstrap capacitor, C
BOOT , is peak charged by the boot-
strap diode, DBOOT , from VDD the power source.
Since the VDD power source is referenced to ground, the
maximum voltage that can build on the bootstrap capacitor is
the sum of VDD and the amplitude of the negative voltage at
the source terminal.
Figure 3. Half-Bridge Application Circuits
Figure 4. VS Waveforms During Turn-off2.4 Cause of Negative Voltage on VS Pin
A well-known event that triggers VS go below COM
(ground) is the forward biasing of the low-side freewheeling
diode, as shown in Figure 5.
Major issues may appear duri ng commutation, just before
the freewheeling diod e starts clamping.
In this case, the inductive parasitic elements, LS1 and LS2,
may push VS below COM, more than as described above or
normal steady-state condition.
The amplitude of negative voltage is proportional to the par-
asitic inductances and the turn-off speed, di/dt, of the switch-ing device; as determined by the gate drive resistor, R
GATE ,
and input capacitance, Ciss, of switching device.
It is sum of Cgs and Cgd, called Miller capacitance.
Figure 5. Step-Down Converter Applications
Figure 6 shows the waveforms of the high-side, N-channel
MOSFET during turn-off.
Figure 6. Waveforms During Turn-offLO COMHO
VSDC SUPPLY
ifreeVDDVB
Q1
Q2RG2RG1
Ls1
Ls2High Side OFF
Freewheeling PathHIN
LINHIN
LINiLoad CBOOTDBOOT RBOOT
CIN
-VStHIN
Freewheelingt
VS -COMQ1VB IN
GNDHO
VSVDDINPUT
D1
HVICVCC
VDCDBOOT
CBOOT
RGATE
CDRV
COUTLS1
LS2C CiLOAD
iFreeA B
GND
– VSVOUT
VDC+VGS,Miller
VDCVBS
Recovery TimeA-Point
B-Point
C-Point
VGS=B-C Point

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 32.5 Effects in the Undershoot Spike on VS Pin
If undershoot exceeds the ab solute maximum rating speci-
fied in the datasheet, the gate drive IC suffers damage or thehigh-side output is temporarily unresponsive to input transi-
tion as shown in Figure 7 and Figure 8.
Figure 7 shows Latch-up case that the high-side output does
not changed by input signal. In this case, short-circuit condi-tion occur on external, main, high-side and low-sideswitches in half-bridge topology.
Figure 7. Waveforms in Case of Latch-up
Figure 8 shows Missing case that the high-side output doesnot responded to input transition. In this case, the levelshifter of the high-side gate driver suffers form a lack of theoperation voltage headroom. This should be noted, butproves trivial in most applications, as the high-side in notusually required to change state immediately following aswitching event.
Figure 8. Waveforms in Case of Signal Missing2.6 Consideration of Latch-up Problem
The most integrated high-voltage gate-drive ICs have para-sitic diodes, which, in forward or reverse break-down, maycause parasitic SCR latch-up. The ultimate outcome of latch-up often defies prediction and can range from temporaryerratic operation to total devi ce failure. The gate-drive IC
may also be damaged indirectly by a chain of events follow-
ing initial overstress. For example, latch-up could conceiv-ably result in both output dr ivers assuming a HIGH state,
causing cross-conduction followed by switch failure and,finally, catastrophic damage to the gate-drive IC. This failuremode should be considered a possible root-cause, if powertransistors and/or gate-drive IC are destroyed in the applica-tion. The following theoretical extremes can be used to help
explain the relationships between excessive V
S undershoot
and the resulting latch-up mechanism.
In the first case, an "ideal boot strap circuit" is used in which
VDD is driven from a zero-ohm supply with an ideal diode
feed VB, as shown in Figure 9. When the high current flow-
ing through freewheeling diode, VS voltage is below ground
level by high di/dt. This time, latch-up risk appears sinceinternal parasitic diode, D
BS of the gate driver ultimately
enters conduction from VS to VB, causing the undershoot
voltage to sum with VDD, causing the bootstrap capacitor to
overcharge, as shown Figure 10.
For example , if VDD=15 V , then VS undershoot in excess of
10V forces the floating supply above 25 V , risking break-down in diode D
BS and subsequent latch-up.
Figure 9. Case 1: Ideal Bootstrap Circuits
Figure 10. VB and VS Waveforms of Case 1INPUT
OUTPUT
Latch-Up Problem
INPUT
OUTPUT
Signal Missing ProblemCOMVB
VS
Gate DriverVDD
DBS
VS
GNDVB
HIGH V BS

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 4Suppose that the bootstrap supply is replaced with the ideal
floating supply, as shown in Figure 11, such that VBS is fixed
under all circumstances. Note that using a low impedanceauxiliary supply in place of a bootstrap circuit can approachthis situation. This time, latch-up risk appears if V
S under-
shoot exceeds the VBS maximum specified in datasheet,
since parasitic diode DBCOM ultimately enters conduction
from COM to VB, as shown in Figure 12.
Figure 11. Case 2: Ideal Floating Supply
Figure 12. VB and VS Waveforms of Case 2
A practical circuit is likely to fall somewhere between these
two extremes, resulting in both a small increase of VBS and
some VB droop below VDD, as shown in Figure 13.
Figure 13. Typical Response of VB and VS
Exactly which of the two ex tremes is prevalent can be
checked as follows. If the VS pins undershoot spike has a
time length that is on order of tenths of nanoseconds; the
bootstrap capacitor, CBOOT , can become overcharged and the
high-side gate-driver circuit has damage by over-voltagestress because it exceeds an absolute maximum voltage(V
BSMAX ) specified in datasheet. Design to a bootstrap cir-
cuit, that does not exceed the absolute maximum rating of
high-side gate driver. 2.7 Effect of Parasitic Inductances
The amplitude of negative voltage is:
To reduce the slope of current flowing in the parasitic induc-
tances to minimize the derivative terms in Equation 1.
For example , if a 10 A, 25 V gate driver with 100nH para-
sitic inductance switches in 50 ns, the negative voltage spikebetween V
S and ground is 20 V .
3. Design Procedure of Bootstrap
Components
3.1 Select the Bootstrap Capacitor
The bootstrap capacitor (CBOOT ) is charged every time the
low-side driver is on and the output pin is below the supplyvoltage (V
DD) of the gate driver. The bootstrap capacitor is
discharged only when the high-side switch is turned on. Thisbootstrap capacitor is the supply voltage (V
BS) for the high
circuit section. The first parameter to take into account is themaximum voltage drop that we have to guarantee when thehigh-side switch is in on state. The maximum allowable volt-age drop (V
BOOT ) depends on the minimum gate drive volt-
age (for the high-side switch) to maintain. If VGSMIN is the
minimum gate-source voltage, the capacitor drop must be:
where:
VDD = Supply voltage of gate driver [V]; and
VF = Bootstrap diode forward voltage drop [V]
The value of bootstrap capacitor is calculated by:
where QTOTAL is the total amount of the charge supplied by
the capacitor.
The total charge supplied by the bootstrap capacitor is calcu-
lated by equation 4.:
where:
QGATE = Total gate charge;
ILKGS = Switch gate-source leakage current;
ILKCAP = Bootstrap capacitor leakage current;
IQBS = Bootstrap circuit quiescent current;
ILK = Bootstrap circuit leakage current;
QLS = Charge required by the internal level shifter, which is
set to 3 nC for all HV gate drivers;
tON = High-side switch on time; andCOMVB
VS
Gate DriverVCC
DBCOMVCC
VS
GNDVB
VB Below COM
VS
GNDVB
VB close to COM
Increased V BS (1)dtdiS S FDBOOT RBOOT L L V V COM ) () ( V2 1 S + − + −= −
GSMIN F DD BOOT V V V V − − = Δ (2)
BOOTTOTAL
BOOTVQC
Δ= (3)
LS ON LKDIODE LK QBS LKGS LKCAP GATE TOTAL Q t II I I I Q Q + ⋅ + + + + + = ) ( (4)

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 5 ILKDIODED = Bootstrap diode leakage current.
The capacitor leakage current is important only if an electro-
lytic capacitor is used; otherw ise, this can be neglected.
For example: Evaluate the bootstrap capacitor value when
the external bootstrap diode used.
Gate Drive IC = FAN7382 (Fairchild)
Switching Device = FCP20N60 (Fairchild)
Bootstrap Diode = UF4007V
DD = 15 V
QGATE = 98 nC (Maximum)
ILKGS = 100 nA (Maximum)
ILKCAP = 0 (Ceramic Capacitor)
IQBS = 120 µA (Maximum)
ILK = 50 µA (Maximum)
QLS = 3 nC
TON = 25 µs (Duty=50% at fs=20KHz)
ILKDIODE = 10 nA
If the maximum allowable voltage drop on the bootstrap
capacitor is 1.0V during the high side switch on state, theminimum capacitor value is calculated by Equation 3.

The value of bootstrap capacitor is calculated as follows:
The voltage drop due to the external diode is nearly 0.7V .
Assume the capacitor charging time is equal to the high-side on-time (duty cycle 50%). Acco rding to different bootstrap
capacitor values, the following equation applies:
Suggested values are within the range of 100 nF ~ 570 nF,
but the right value must be se lected according to the applica-
tion in which the device is used . When the capacitor value is
too large, the bootstrap charging time slows and the low-side on time might be not long enough to reach the bootstrap volt-age.3.2 Select the Bootstrap Resistor
When the external bootstrap re sistor is used, the resistance,
RBOOT , introduces an addi tional voltage drop:
where:
ICHARGE = Bootstrap capacitor charging current;
RBOOT = Bootstrap resistance; and
tCHARGE = Bootstrap capacitor charging time (the low-side
turn-on time).
Do not exceed the ohms (typically 5~10 Ω) that increase the
VBS time constant. This voltage drop of bootstrap diode
must be taken into account when the maximum allowablevoltage drop (V
BOOT ) is calculated. If this drop is too high or
the circuit topology does not allow a sufficient chargingtime, a fast recovery or ultra-fa st recovery diode can be used.
4. Consideration of Bootstrap
Application Circuits
4.1 Bootstrap Startup Circuit
The bootstrap circuit is useful in high-voltage gate driver, as
shown in Figure 1. However, it has a initial startup and lim-ited charging a bootstrap capac itor problem when the source
of the main MOSFET (Q1) and the negative bias node ofbootstrap capacitor (C
BOOT ) are sitting at the output voltage.
Bootstrap diode (DBOOT ) might be reverse biased at startup
and main MOSFET (Q1) has a insufficient turn-off time for
the bootstrap capacitor to main tain a required charge, as
shown in Figure 1.
In certain applications, like in battery chargers, the output
voltage might be present before input power is applied to theconverter. Delivering the init ial charge to the bootstrap
capacitor (C
BOOT ) might not be possible, depending on the
potential difference between the supply voltage (VDD) and
output voltage (VOUT) levels. Assuming there is enough
voltage differential between input voltage (VDC) and output
voltage (VOUT), a circuit comprised of startup resistor
(RSTART ), startup diode (DSTART ), and Zener diode (DZ) can
solve the problem, as shown in Figure 14. In this startup cir-cuit, startup diode D
START serves as a second bootstrap
diode used for charging the bootstrap capacitor (CBOOT ) at
power up. Bootstrap capacitor (CBOOT ) is charged to the
Zener diode of DZ, which is supposed to be higher than the
driver's supply voltage (VDD) during normal operation. The
charge current of the bootstr ap capacitor and the Zener cur-
rent are limited by the startup re sistor. For best efficiency,
the value of startup resistor should be selected to limit thecurrent to a low value, since the bootstrap path through thestartup diode is permanently in the circuit.][102.105)103()}1025()10101050 10 120 10 100{()1098(
99 6 96 6 9 9
CQTotal
−− − −− − − −
× =×+ × × ×+×+ × + × + × =
(6)
][1051102.1059
nFVQC
BOOTTOTAL
BOOT ≅×=Δ=−
(7)
(8) VBOOTΔQTOTAL
CBOOT––––––– – =
100nF VBOOTΔ 1.05 V=
150nF VBOOTΔ 0.7 V=
220nF VBOOTΔ 0.48 V=
570nF VBOOTΔ 0.18 V=CHARGEBOOT CHARGE
RBOOTtR IV•= (5)

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 6Figure 14. Simple Bootstrap Startup Circuit
4.2 Resistor in Series with Bootstrap Diode
In the first option, the bootstr ap circuit includes a small
resistor, RBOOT , in series with bootstrap diode, as shown in
Figure 15. The bootstrap resistor, RBOOT , provides current
limit only during a bootstrap charging period which repre-sents when the V
S goes below the IC supply voltage, VCC, or
is pulled down to ground (the low-side switch is turned onand the high-side switch is turned off). The bootstrap capaci-tor, C
BOOT , charge through the bootstrap resistor, RBOOT ,
and diode, DBOOT , from the VCC power supply. The boot-
strap diode must have a break-down voltage (BV) larger thanV
DC and a fast recovery time to minimize the amount charge
feedback from the bootstrap capacitor to VCC power supply.
Figure 15. Adding a Series Resistor with DBOOT
This method has the advantage of being simple for limitingthe current when the bootstrap capacitor is initially charged,
but it has some limitations. Duty-cycle is limited by therequirement to refresh the char ge in the bootstrap capacitor,
C
BOOT , and there are startup problems. Do not exceed the
ohms (typically 5~10 Ω) that would increase the VBS time
constant. The minimum on-time for charging the bootstrap
capacitor or for refreshing its charge must be verified againstthis time constant. The time constant depends on the valuesof bootstrap resistance, capacitance, and duty cycle ofswitching device calculated in following equation:
where R
BOOT is the bootstrap resistor; CBOOT is the boot-
strap capacitor; and D is the duty cycle. For example, if RBOOT =10, CBOOT =1 µF, and D=10 %; the
time constant is calculated in following equation:
Even with a reasonably larg e bootstrap capacitor and resis-
tor, the time constant may be large. This method can mitigatethe problem. Unfortunately, the series resistor does not pro-vide a foolproof solution against an over voltage and itslows down the recharge pro cess of the bootstrap capacitor.
4.3 Resistor Between VS and VOUT
In the second option, the bootstrap circuit includes a small
resistor, RVS, between VS and VOUT, as shown in Figure 16.
Suggested values for RVS are in the range of some ohms.
Figure 16. Adding RVS in Bootstrap Circuit
The RVS works as, not only bootstrap resistor, but also turn-
on and turn-off resistors, as shown in Figure 17. The boot-strap resistor, turn-on, and turn-off resistors are calculated bythe following equations:
Figure 17. Current Paths of Turn-on and Turn-off INPUTRBOOT DBOOT
CBOOT
COUT DLQ1
VOUTVDC VDD
DSTART RSTART
DZ
RGATE
COMHIN
VSVB
HOVDD
DBOOT
HIN
CBOOTVCC
RBOOT
Q1
R1
R2VB
HIN
COMHO
VS
LOLINVCC
R3
R4VDC
Q2LIN
LoadC1
(9) τRBOOTCBOOT⋅
D–––––––––––––- s [] = (10) τRBOOTCBOOT⋅
D–––––––––––––-10 16–⋅
0.1–––––– 1 0 0 μs[] == =
Q1VB IN
GNDHO
VSVCC
L1IN
D1
HVICVCC VDC
DBOOT
CBOOT
RGATE
CDRV
COUTRBOOT
RVSVOUT
RBOOT∗ RBOOTRVS+ =
(11)
RON∗ RGATERVS+ =
(12)
ROFF∗ RGATERVS+ =
(13)
Q1VB
IN
GNDHO
VSVCC
L1IN
D1VCC
DBOOT
CBOOT
RGATE
CDRV
COUTRBOOT
RVSVOUTIBCHG
ITURN-ON
ITURN-OFF

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 74.4 Clamping Diode for VS and Relocation
Gate Resistor
In the third option, the bootstrap relocates a gate resistor
between VS and VOUT and adds a low forward-voltage drop
Schottky diode from ground to VS, as shown in Figure 18.
The difference between VB and VS should be kept inside the
absolute maximum specification in the datasheet and mustbe satisfied by the following equation:
Figure 18. Clamping Structure
4.5 Relocated Gate Resistor; Double Purpose
The gate resistor sets the turn-on and turn-off speeds in theMOSFET and provides current limiting for the Schottkydiode during the negative voltage transient of the source ter-minal of the main switch. In additional, the bootstrap capaci-
tor is protected against over voltage by the two diodesconnected to the ends of C
BOOT . The only potential hazard
by this circuit is that the ch arging current of the bootstrap
capacitor must go through gate resistor. The time constant ofC
BOOT and RGATE slows the recharge process, which might
be a limiting factor as the PWM duty cycle.
The fourth options includes relocating a gate resistor
between VS and VOUT and a clamp device should be posi-
tioned between ground and VS, as shown in Figure 19, where
a Zener diode and a 600 V diode are placed. The Zener volt-age must be sized accordi ng to the following rule:
Figure 19. Clamping Structure with Zener Diode5. Choose Current Capability HVIC
The approximate maximum gate charge QG that can be
switched in the indicated time for each driver current rating
is calculated in Table 1:
Table 1. Example HVIC Current-Drive Capability
Note:
1. For a single 4 A, parallel th e two channels of a dual 2 A!
For example , a switching time of 100 ns is:
1 % of the converter switching period at 100 KHz;3 % of the converter switching period at 300 KHz; etc.
1. Needed gate driver current ratings depend on what gate
charge Q
G must be moved in switching time tSW-ON/OFF
(because average gate curr ent during switching is IG):
2. The maximum gate charge, QG, is read from the MOSFET
datasheet.
If the actual gate-drive voltage VGS is different from the test
condition in the specifications table, use the VGS vs. QG
curve instead. Multiply the da tasheet value by the number
of MOSFETs in parallel.
3. tSW_ON/OFF is how fast the MOSFET should be switched.
If unknown, start with 2% of the switching period tSW:
If channel (V-I) switching loss is dominated by one switch-
ing transition (turn-on or turn -off), size the driver for that
transition. For clamped inductive switching (the usual case),channel switching loss for each transition is estimated as:
where V
DS and ID are maximum values during the switching
interval.
4. The approximate cu rrent drive capability of gate driver
may be calculated like below
(1) Sourcing Current Capability (Turn-on) max _abs BS S B V V V < − (14)
Q1VB IN
GNDHO
VSVCC
L1IN
D1
HVICVCC VDC
DBOOT
CBOOT
RGATECDRV
COUT DSCHTVOUT
(15) VBVS–VBS ABSMAX,<
Q1VB IN
GNDHO
VSVDD
L1IN
D1
HVICVCC VDC
DBOOT
CBOOT
RGATECDRV
COUTVOUT
D2DZNeeded
Current
RatingSwitching Time (tSW_ON/OFF )
100 ns 50 ns
Maximum Gate Charge (QG,MAX )
2 A 133 nC 67 nC4 A 267 nC 133 nC
9 A 600 nC 300 nC
offon swG
SWAVGtQI
/ _.. = (16)
(17) tSWON OFF ,0.02 tSW×0.02
fSW–––– ==
(18) ESW0.5VDSID× tSW× Joules =
(19) ISOURCE1.5QG
tSW ON,––––––-× ≥

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 8(2) Sinking Current Capability (Turn-off)
where:
QG = MOSFET gate charge at VGS = VDD;
tSW_ON/OFF = MOSFET switch turn-on / turn-off time; and
1.5 = empirically determined factor (influenced by delay
through the driver input stages and parasitic elements).
6. Gate Resistor Design Procedure
The switching speed of the out put transistor can be con-
trolled by values of turn-on and turn-off gate resistors con-trolling the turn-on and turn-off current of gate driver. Thissection describes basic rules for values of the gate resistors
to obtain the desired switching time and speed by introduc-ing the equivalent output resistor of the gate driver. Figure20 shows the equivalent circui t of gate driver and current
flow paths during the turn-on and turn-off, including a gatedriver and switching devices.
Figure 20. Gate Driver Equivalent Circuit
Figure 21 shows the gate-charge transfer characteristics of
switching device during turn-on and turn-off.
Figure 21. Gate Charge Transfer Characteristics6.1 Sizing the Turn-On Gate Resistor
Turn-on gate resistor, Rg(ON) , can be chosen to obtain the
desired switching time by using switching time, tsw. To
determine a value of resistor using the switching time, sup-ply voltage, V
DD (or VBS), equivalent on resistance
(RDRV(ON) ) of the gate driver, and switching device parame-
ters (Qgs, Qgd, and Vgs(th)) are needed.
The switching time is defined as the time spen t to reach the
end of the plateau voltage (a total Qgd + Qgd has been pro-
vided to the MOSFET gate), as shown in Figure 21.
The turn-on gate resistor calculated as follows:
where Rg(ON) is the gate on resistance and RDRV(ON) is the
driver equivalent on resistance.
6.2 Output Voltage Slope
Turn-on gate resistor Rg(ON) can be determined by control
output slope (dVOUT/dt). While the output voltage has a non-
linear behavior, the maximum output slope can be approxi-mated by:
Inserting the expression yielding I
g(avr) and rearranging:
where Cgd(off) is the Miller effect capacitor, specified as Crss
in the datasheet.
6.3 Sizing the Turn-Off Gate Resistor
The worst case in sizing the turn -off resistor is when the
drain of the MOSFET in turn-off state is forced to commu-
tate by external events.
In this case, dV/dt of the output node induces a parasitic cur-
rent through Cgd flowing in RG(OFF) and RDRV(OFF) , as
shown in Figure 22
The following describes how to size the turn-off resistor
when the output dv/dt is cau sed by the companion MOSFET
turning-on, as shown in Figure 22.
For this reason, the off-resistance must be sized according to
the application worst case. Th e following equation relates
the MOSFET gate threshold voltage to the drain dv/dt: (20) ISINK1.5QG
tSW OFF,––––––– – × ≥
VDC
DRIVER
VDD
GND
DRIVERRGATE
CgdCgsCgd
Cds112VB
VS
LOHOTurn -On
Turn -OffON
OFF
ONOFF
VDDVBS
CgsRG(ON)
2HVIC
VOUT
RG(OFF)dVOUT
dtdVOUT
dtRDRV(ON)
RDRV(OFF
)
(21) Iga v r()QgsQgd+
tSW–––––––– – =
(22) RTOTALRgO N()RDRV ON ()+VDDVgs+
Iga v r()––––––––– – ==
(23)dVOUT
dt–––––– -Iga v r()
Cgd off()––––––-=
(24) RTOTALVDDVgs th()–
Cgd off()dVOUT
dt–––––– – ⋅––––––––––––––=

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 9Figure 22. Current Paths: Low-Side Switch Turned Off,
High-Side Switch Turned On
Rearranging the equation yields:
6.4 Design Example
Determine the turn-on and off gate resistors using the Fairch-
ild MOSFET with FCP20N60 and gate driver withFAN7382. The power MOSFET of FCP20N60 parametersare as follows:
Q
gs=13.5 nC, Qgd=36 nC, Cgd=95 pF, VGS(th) =5 V ,
VGS(th)MIN =3 V
6.4.1 Turn-On Gate Resistance
1) If the desired switching time is 500 ns at VDD=15 V, the
average gate charge current is calculated as:
The turn-on resistance value is about 58 Ω.
2) If dVout/dt=1 V/ns at VDD=15 V , the total gate resistor is as calculated as:
The turn-on resistance value is about 62 Ω.
7.4.2 Turn-Off Gate Resistance
If dVout/dt=1 V/ns, the turn-off gate resistor is calculated as:
8. Power Dissipation Considerations
8.1 Gate Driver Power Dissipation
The total power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver losses
are comprised of the static a nd dynamic losses related to the
switching frequency, output load capacitance on high- and
low-side drivers, and supply voltage, VDD.
The static losses are due to the quiescent curr ents from the
voltage supplies VDD and ground in low-side driver and the
leakage current in the level shif ting stage in high-side driver,
which are dependent on the voltage supplied on the VS pin
and proportional to the duty cycle when only the high-sidepower device is turned on.
The dynamic losses are defined as follows: In the low-side
driver, the dynamic losses are due to two different sources.
One is due to whenever a load capacitor is charged or dis-
charged through a gate resistor, half of energy that goes intothe capacitance is dissipated in th e resistor. The losses in the
gate drive resistance, internal an d external to the gate driver,
and the switching loss of the internal CMOS circuitry. Also,the dynamic losses of the high-side driver have two differentsources. One is due to the leve l-shifting circuit and one due
to the charging and discharg ing of the capacitance of the
high side. The static losses are neglected here because thetotal IC power dissipation is mainly dynamic losses of gatedrive IC and can be estimated as:
Figure 23 shows the calculated gate driver power dissipation
versus frequency and load capacitance at V
DD=15 V . This
plot can be used to approximate the power losses due to the-
gate driverVDC
DRIVER
VDD
GND
DRIVERRGATE
CgdCgsCgd
Cds12VB
VS
LOHOTurn -On
Turn -OffON
OFF
ONOFF
VDDVBS
CgsRG( ON)HVIC
RG( OFF)RDRV(ON)
RDRV(OFF
)dVOUT
dt
iLOADLoad
dtdVC R Ri R R V
out
gd drv OFFgg OFF DRV OFFg thgs
× + =× + ≥
) {(} ) {(
) ( ) () ( ) ( )(
(25)
)()(
g(off)Rdrv
out
gdthgsR
dtdVCV−
⋅≤ (26)
][995005.13 36
)( mAnsnC nC
tQ QI
SWgd gs
avrg =+=+= (27)
][10199515
)()(Ω =−=−=mA IV VR
avrgthgs DD
Total (28)
][4335015
) ( Ω ≈ = =mAV
IVR
SOURCEDD
ON DRV (29)][10510 1095515
9 12
)()(Ω =× ×−=
⋅−=−
dtdVCV VR
OUT
offgdthGS DD
Total (30)
][4335015
) ( Ω ≈ = =mAV
IVR
SOURCEDD
ON DRV(31)
][2365015
) ( Ω ≈ = =mAV
IVR
SINKDD
OFF DRV (32)
6.8 2310 10953R9 12 )(min)(
g(off) = −× ×= −
⋅≤− drv
out
gdthgsR
dtdVCV
(33)
][ 22W Vf C PDD s L DGATE ×× ×= (34)

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 10
Figure 23. Gate Driver Total Power Dissipation
The bootstrap circuit power dissipation is the sum of the
bootstrap diode losses and the bootstrap resistor losses if anyexist. The bootstrap diode loss is the sum of the forward biaspower loss that occurs while charging the boot strap capacitor
and the reverse bias power loss that occurs during reverserecovery. Since each of these events happens once per cycle,
the diode power loss is proportional to switching frequency.Larger capacitive loads require more current to recharge the
bootstrap capacitor, resulting in more losses.
Higher input voltages (V
DC) to the half-bridge result in
higher reverse recovery losses. The total IC power dissipa-tion can be estimated by summing the gate driver losses withthe bootstrap diode losses, except bootstrap resistor losses.
If the bootstrap diode is within the gate driver, add an exter-
nal diode in parallel with the internal bootstrap diodebecause the diode losses can be significant. The external
diode must be placed close to the gate driver to reduce para-sitic series inductance and si gnificantly lower forward volt-
age drop.
8.2 Package Thermal Resistance
The circuit designer must provide:
• Estimate power dissipation of gate driver package
• The maximum operating junction temperature TJ,
MAX,OPR , e.g., 120 °C for these drivers if derated to 80 %
of TJ,MAX =150 °C.
• Maximum operating lead temperature TL,MAX,OPR ,
approximately equal to th e maximum PCB temperature
underneath the driver, e.g., 100 °C.
• Maximum allowable junction- to-lead thermal resistance
is calculated by:9. General Guidelines
9.1 Printed Circuit Board Layout
The layout for minimized parasitic inductances is as follows:
• Direct tracks between switches with no loops or deviation.
• Avoid interconnect links. These can add significant
inductance.
• Reduce the effect of lead-i nductance by lowering package
height above the PCB.
• Consider co-locating both power switches to reduce track
length.
• Placement and routing for d ecoupling capacitor and gate
resistors as close as possible to gate drive IC.
• The bootstrap diode as close as possible to bootstrap
capacitor.
9.2 Bootstrap Components
The bootstrap resistor (RBOOT ) must be considered in sizing
the bootstrap resistance and the current developed during ini-tial bootstrap charge. If the resi stor is needed in series with
the bootstrap diode, verify that V
B does not fall below COM
(ground), especially during st artup and extremes of fre-
quency and duty cycle.
The bootstrap capacitor (CBOOT ) uses a low-ESR capacitor,
such as ceramic capacitor. The capacitor from VDD to COM
supports both the low-side dr iver and bootstr ap recharge. A
value at least ten times higher than the bootst rap capacitor is
recommended.
The bootstrap diode must use a lower forward voltage drop
and switching time as soon as possible for fast recovery,
such as ultra-fast.0.1 1 10 100 10000.010.11
Power [W]
Switching frequency [kHz]CLOAD=4400PF
CLOAD=470PFCLOAD=1000PFCLOAD=2200PFAt V DD = 15V
PKGL J
JLPT Tmax, max,
max,−=θ (35)

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 11Table 2. Summary of High-Si de Gate Drive Circuitry
Method Basic Circuit Advantages & Limitations
High-Side Gate Driv ers for P-Channel
Direct DriveCan be implemented if the maximum input voltage is
less than the gate-to-source break down voltage of
the device.
Open CollectorSimple method, but is no t suitable for driving
MOSFET directly in a high-speed application.
Level-Shifted DriveSuitable for high-speed application and works
seamlessly with re gular PWM controller.
High-Side Gate Driv ers for N-Channel
Direct DriveEasiest high-side application the MOSFEF and can
be driven directly by the PWM controller or by a
ground referenced driver, but it must meet two conditions, as follows:
Floating Supply
Gate Drive Cost impact of isolated s upply is significant. Opto-
coupler tends to be relati vely expensive, limited in
bandwidth, and noise sensitive.
Transformer
Coupled DriveGives full gate control for an indefinite period of time,
but is somewhat limited in switching performance.
This can be improved with added complexity.
Charge Pump
DriveThe turn-on times tend to be long for switching
applications. Inefficiencies in the voltage multiplication circuit may require more than low
stages of pumping.
Bootstrap DriveSimple and inexpensive wit h limitations; such as,
the duty cycle and on-time are both constrained by the need to refresh the bootstrap capacitor.
Requires level shift, with the associated difficulties.Q1VCC
L1
D1PWM
ControllerVCC
RGATE
COUTVOUT
VOUTGNDOUT
Q1
GNDVCC
L1
D1PWM
ControllerVCC VDC
RGATE
COUTVOUT
VOUTOUTRPULL
Q1
VCCL1
D1PWM
ControllerVCCVDC
RBASE
COUTVOUT
VOUTR2RGATER1
GNDOUTQINV
Q1VCC
L1
D1PWM
ControllerVCC VDC
RGATE
COUTVOUT
VOUTGNDOUT
DSCHT
MillerGS CC DC MAXGS CC V V V and V V, , − < <
Q1VCC
L1PWM
ControllerVCC VDC
RGATE
COUTVOUT
VOUTQ2RGATE
GNDFloating
Supply
HO
Opto
LO
Q1
VCC
L1PWM
ControllerVCC VDC
RGATE
COUTVOUT
VOUTQ2T1
RGATECBLOCK
GNDOUT2OUT1
Q1
GNDVCC
L1
D1PWM
ControllerVCC VDC
COUTVOUT
VOUTOUT
Q1VB IN
GNDHO
VSVCC
L1IN
D1
HVICVCC VDC
DBOOT
CBOOT
RGATE
CDRV
COUTVOUT

AN-6076 APPLICATION NOTE
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 12Consideration Points of Bootstrap Circuit Problem
Remedies of Bootstrap Circuit Problem Q1VB IN
GNDHO
VSVCCINPUT
D1
HVICVCC
VDCDBOOT
CBOOT
RGATE
CDRV
COUT
The amplitude of the negati ve voltage is proportional
parasitic inductances and the turn-off speed (di/dt) of
the switching device, Q1, which is determined by gate
resistor, R GATE, and input capacitance, C iss.LS1
LS2
Latch-up,
propagation signal
missing and over-
voltage across the
bootstrap
capactorIf V S goes significantly below
ground, the gate driver can
have serious troubles.Negative voltage transient
at high-side switch turn-off.C CVDC+VGS,Miller
VDCVBS
Recovery TimeA-Point
B-Point
C-Point
VGS=B-C Point
iLOAD
iFreeA B
GND
– VSVBS= (V CC -VFBD ) – (-V S)

AN-6076 APPLICATION NOTE
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© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.4 • 12/18/14 13

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