Leakage Current Reduction Using Power Gating And Mtcmos

Leakage Current Reduction Using Power Gating and MTCMOS

B.Sudharani

Assistant Professor: Department of ECE

Sri Venkateswara College of Engineering

Tirupati, Andhrapradesh, India

[anonimizat]

V.Madhurima

Assistant Professor: Department of ECE

Sri Venkateswara College of Engineering

Tirupati, Andhrapradesh, India

[anonimizat]

Abstract— This paper deals different power gating techniques in circuit design level. Power gating technique is much easier to implement but offers only a limited leakage reduction. As technology scaling down into the nanometer ground bounce noise and heat dissipation immunity are becoming important metric is comparable with the performance analysis and design of logic circuits. Due to the power dissipation limitation of transistors, processor designs have increasingly relied on new architectures to improve performance instead of feature size scaling alone. With the improvement of semiconductor technologies, more processing units can be integrated on a single chip, to satisfy the growing computation demands from high performance applications there is an investigation of new technology to increase the performance.

Keywords—Leakage current, MTCMOS, Power Gating.

Introduction

In each combinational block in the conventional asynchronous four-phase bundled-data pipeline[10] is provided by both a header and a footer sleep transistor. When the latch controller in a pipeline stage detects valid input data, it absorbs the data in the data latch and turns on the sleep transistors. So, that the combinational block can wake up and process the input data to generate the output data. When the output data are received by the next pipeline stage, an acknowledge signal is sent back to this stage, and the latch controller can turn off the sleep transistors of the associated combinational block to reduce leakage dissipation. Matched Delay element is matched to at least the worst-case delay of the Combinational Block. This is necessary to ensure the computed data values and the output request signal arrives at the input of the next stage around the same time, and trigger a new round of handshaking events. In conventional asynchronous four phases bundled data logic pipeline is a simple technique to reduce power dissipation; however the hardware overhead is large and still suffers with leakage dissipation. A new solution to detect arriving asynchronous activity, which related to an automatic power regulation [11], effectively decreases the supply voltage and thus the leakage current. To regulate the leakage of an asynchronous unit and in order to power down the asynchronous logic unit when in standby mode voltage regulator is used. Activity recognition on the transactions in channels is perform using channel monitors. When no more activity is detected, the voltage regulator powers off the asynchronous logic unit in standby mode and hence reducing the leakage power. When new incoming activity is detected, the voltage regulator powers on the asynchronous logic in common mode, with no additional software control and at minimal latency cost. Due to their robustness to operating conditions, asynchronous circuits can be easily complete at low voltage for power down. The proper protocol must be chosen in order to detect traffic with a fast and unfailing detection. The second constraint is regarding the voltage regulator and the definition of the standby mode. It is a chain of inverters, with the logical part designed using 2N-2N2P logic, whereas the control part of the C&R block is made of pass gate logic and regeneration part is made of conventional CMOS logic. Each stage in an AAL circuit consists of an adiabatic gate, which implements the logic function of this stage, and a control and regeneration (C&R) block, whose output supplies power to the associated adiabatic logic gate. When the C&R block detects that the input to the adiabatic gate becomes valid, the output of the C&R block transits to HIGH, and the adiabatic gate can acquire power to evaluate its output; when the C&R block detects that the input to the adiabatic gate becomes empty, the output of the C&R block transits to LOW, and the adiabatic gate is not powered and becomes idle. test chip consists of AAL logic circuits has been designed and fabricated in CMOSP18 0.18um technology as a proof of concept. It consists of closed loop chain of different adiabatic NAND gates as the logical block and conventional CMOS OR as C&R block.

Optimizations of the logic delays and more precise control over the slope of the control signal can make the AAL a more power efficient logic. Evolution of devices with technologies such as SOI or MEMS based switches to limit the leakage currents at lower speeds will be very helpful for the power efficient operation of our proposed design and the efficient low frequency operation of adiabatic logic circuits. In AAL circuit consists of a adiabatic gate which implements the logic function and control and regeneration block supplies output to the associated adiabatic gate. In this the synchronization between neighboring stages is accomplished via a unidirectional control signal rather than bidirectional handshake signal so it suffers with diverse propagation delay.

In the fine grained MTCMOS circuit is AFPL the logic blocks become active only when performing valuable operations, and the idle logic blocks were not powered and have negligible leakage power dissipation. With fine-grain power gating, the AFPL approach has more opportunities to reduce leakage at run-time than other coarse-grain power gating-techniques. The AFPL [12] circuit employs ECRL logics to construct its logic blocks to avoid the occurrence of the short-circuit current from VDD to the ground, and to eliminate the requirement for additional standalone pipeline latches. AFPL-PCR pipeline can enter into the sleep mode early on to diminish leakage dissipation once its output has been received by the downstream pipeline stage. Two techniques of circuit simplification have been developed to mitigate the hardware overhead of the AFPL circuit.

Although the AFPL-PCR implementation has the advantage of lower power dissipation, it suffers the problem of a lower maximum sustainable throughput rate. As technology scales into the nanometer regime ground bounce noise and heat dissipation immunity are becoming important metric is comparable with the importance to leakage current, active power, delay and area for the analysis and design of logic circuits

In section II describes the System architecture. In section III Simulation results has explained

System Architecture

Low power consumption, speed of the system and the small area are the three main factors for increasing the performance of a circuit. Delay and power dissipation of a circuit have also emerged as major concerns of designers and depend on the number of transistors used in the circuit. The scaling of process technologies to nanometer regime has resulted in a rapid increase in leakage power dissipation [6] & [7]. Hence, it has become important to expand design techniques to reduce the static power dissipation during period of inactivity. The power decrease must be achieved without degrading the performance which makes it harder to reduce leakage during normal operation. On the other hand, there are various techniques for reducing leakage power in sleep or standby mode. One of the most promising mechanisms for reducing leakage energy is power gating, whereby leakage energy is saved by cutting the supply voltage to idle circuits. Power gating is a power-saving technique; the supply voltage transistor or an nMOS transistor [4]. In the active mode, the sleep transistor is turned on to retain the functionality of the circuit. In the sleep mode, the sleep transistor is turned off, and thus cutting off the leakage path. Moreover, latest technologies with smaller dimensions and lower supply voltages contribute to lowering power dissipation. In this paper MOS full adder circuit is used to give details the concept of reducing power consumption, which also explains the advantages of CMOS implementation and various design techniques used to make it more efficient [13]. Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems. The design of a full adder having low-power consumption results of great interest for the implementation of modern digital systems. Also, CMOS approach helps in accommodating large number of transistors on a single chip.

Power Consumption in CMOS VLSI Circuits

The most important performance parameters for VLSI systems are speed and power consumption. Previously, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously. There are three major components of power dissipation in CMOS circuits: switching power, short circuit power and static power [8]. Reducing any of these components will end up with low power consumption of the whole system. The first two components are referred to as dynamic power. Dynamic power accounts for the majority of the total power consumption in digital CMOS VLSI circuits. The current pulse from VDD to GND results in a short circuit dissipation. Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. The total power is given by the following equation.

Ptotal=Vdd2.Fclk.Cload+Vdd.ΣiIisc+Vdd.Il (1)

Where Vdd is the power supply voltage, Fclk is the system clock frequency, Cload is the load capacitance, Ii sc is the short-circuit current at node I and II is the leakage current. Static power is also known as idle power or leakage power. To understand how leakage current arises, one must understand how transistors work. A transistor regulates the flow of current between two terminals called the source and the drain. Between these two terminals is an insulator, called the channel that resists current. As the voltage at a third terminal, the gate, is increased, electrical charge accumulates in the channel, reducing the channel’s resistance and creating a path along which electricity can flow. Once the gate voltage is high then it allows the normal flow of current between the source and the drain. The threshold at which the gate’s voltage is high enough for the path to open is called the threshold voltage. As the equation that follows illustrates, leakage power consumption is the product of the supply voltage (V) and leakage current (Ileak), or parasitic current, that flows through transistors even when the transistors are turned off.

Pleak = V Ileak (2)

B. Conventional CMOS logic style

Conventional CMOS Logic is a type of static logic style. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. CMOS circuits are constructed that all pMOS transistors must have either an input from the voltage source or from another pMOS transistor. likewise, all nMOS transistors must have either an input from ground or from another nMOS transistor. The composition of a pMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an nMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief spike in power consumption.

In short, the outputs of the pMOS and nMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS circuits' output is the inverse of the input. The power supplies for CMOS are called VDD and VSS, or VCC and GND depending on the manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the drain and source supplies. An important characteristic of a CMOS circuit is the duality that exists between its pMOS transistors and nMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's laws based logic, the pMOS transistors in parallel have corresponding nMOS transistors in series while the pMOS transistors in series have corresponding nMOS transistors in parallel.

Figure 1: Conventional CMOS principle

An advantage of CMOS over nMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in nMOS logic. CMOS logic dissipates less power than nMOS logic circuits because CMOS dissipates power only when switching. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise. Conventional CMOS devices work over a range of −55 °C to +125 °C and presents robustness against voltage scaling and high noise margins, so allowing a reliable operation at low voltages. Other advantages of the CMOS logic style are its robustness against voltage scaling and transistor sizing and thus reliable operation at low voltages and arbitrary transistor sizes. Input signals are connected to transistor gates only, which facilitates the usage and characterization of logic cells. The layout of CMOS gates is straightforward and efficient due to the complementary transistor pairs. Basically, CMOS fulfils all the requirements regarding the ease-of-use of logic gates.

C. Ground bounce noise

Ground bounce defines a condition when a device's output transition from high to low and makes a voltage change on other pins. It is usually seen on high density VLSI. Ground bounce is nothing but the voltage fluctuation between the ground pin on a component package and the ground reference level on the component die. Essentially it is caused by a sudden current through the lead inductance of the package. The problem is cause by the large current flow through the ground pin which develops a voltage drop over the lead inductance. This voltage drop on the ground line creates two main problems: first it raises the chip off ground potential which in turn increases the devices input threshold level, and secondly increases the voltage level on an output pin which is not switching. This is also called Simultaneous Switching Noise [2].

Figure 2: Ground bounce noise

Fig. 2 shows the graphical representation of ground bounce noise. In this phenomenon, when the gate is turned on the silicon in the immediate vicinity of the emitter is pulled high, sometimes by several volts, thus raising the local ground, as perceived by the transistor, to a value significantly above true ground. Relative to this local ground, the base voltage can go negative, thus shutting off the transistor. Otherwise it is the large sudden current that flows through the power and ground rails during standby-to-active mode transition. This results in

long period of power and ground rails’ fluctuation, due to the inductance of the off-chip packaging and the on-chip power grids. This resonance noise sometimes referred to as ground bounce noise or simultaneous switching noise [3]. This noise occurs in both power networks during mode transition, and the fluctuation in the power network.

D. Circuit design D.1 Conventional CMOS 28T full adder design

The 28 Transistor full adders is the pioneer CMOS traditional adder circuit. This is considered as a base case throughout this project. All comparisons are done with this base case. Conventional CMOS implementation consists of two functional blocks pull-up and pull-down. Pull-up functional block is implemented with p-channel MOS transistors and pull-down functional block is implemented with n-channel MOS transistors. It is observed in the conventional adder circuit that the transistor ratio of pMOS to nMOS is 2 for an inverter and remaining blocks also followed the same ratios when we considered the remaining blocks as an equivalent inverters.

Figure 3: Conventional CMOS full adder

Figure 4: Equivalent circuit for conventional CMOS full adder

Fig. 3 shows the conventional CMOS 28 transistor adder [3]. The first 12 transistors of the circuit produce the CARRY and the remaining transistors produce the SUM outputs. Therefore the delay for computing CARRY is added to the total propagation delay of the SUM output. Base case is considered as individual block as shown in Fig. 4. Each block has been treated as an equivalent inverter. The same inverter ratio is maintained on each block. These sizing will reduce the standby leakage current greatly because sub-threshold current is directly proportional to the W/L ratio of transistor. The MOS transistor’s performance varies with its channel length and channel width. On the other hand, these reduced sizes will reduce the area occupied by the circuit. This will reduce the silicon chip area and obviously there will be a reduction in the cost.

SIMULTION RESULTS

Circuit simulations are done by using DSCH2. Fig. 5 shows the simulation result of a conventional CMOS full adder.

Figure 5: Circuit simulation for CMOS FA

Active Power

The power dissipated by the circuit when the circuit is in active state. Considered simulation time to calculate active power is 10ns for CMOS full adder and 100ns for ALU. Input vectors have been given in such a way that it covers almost all input vector combinations. The same vectors and simulation time has been given to base case to compare the results with different CMOS technologies and the result is shown in Table.1.

Table 1: Power & Area comparison with different CMOS technologies

Area

The layouts are used to calculate the areas of proposed designs [9]. Layouts of proposed full adder circuit and ALU are shown in Fig.5 and the simulation results are shown in Fig.6. Along with technology scaling down the area of the CMOS full adder and the ALU circuits are reduced and the result is shown in Table.2

The proposed work consists of the comparison of different power gating techniques such as coarse-grained power gating with footer and header switches and fine-grained power gating with footer and header switches. Also for improving the peak of the ground bounce noise reduction staggered-phase damping technique is used.

Table 2: Comparison of different power gating techniques

Grounded Bounce Noise Reduction

Power gating is an effective method to reduce leakage power during the circuit in sleep mode; it introduces the ground bounce problem and has considerable energy consumption during the mode transitions.

Figure 6: Noise reduction in CMOS full adder

CONCLUSIONS

Low power consumption is targeted at the circuit design level. This project intends to reduce the ground bounce noise caused by large discharge current through a sleep transistor during the mode transition of the power gating structure. Here different power gating structures are proposed to reduce the magnitude of voltage glitches in the power distribution network. In this work, low leakage 1 bit full adder cell is proposed for low ground bounce noise. Logic design and circuit design of conventional CMOS full adder having eight functions are completed and also verified the simulation results. Also the power and area comparison is done by using the automatically generated layouts. After applying power gating technique active power is reduced by 19% in comparison to CMOS full adder. Hence the noise immunity of proposed circuits are also reduced. For calculating the area layout design of CMOS full adder has done. The proposed 1-bit full adder has performed by using DSCH2 and Microwind2 with different CMOS technologies.

Acknowledgment

We would like to thank the management & Principal of Sri Venkateswara College of Engineering for their support & sponsoring.

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