Electrical modelling of Through Silicon Vias (TSVs) [602642]

Electrical modelling of Through Silicon Vias (TSVs)
and their impact on a CMOS circuit:
Ring Oscillator
M.A. Benkechkache, S. Latreche
Laboratory Hyperfrequencies and Semiconductors
Dept. Electronics, University Constantine1, Algeria
Email: [anonimizat]
Email: [anonimizat].F. Dalla Betta, L. Pancheri
Laboratory Micro and Nano Systems
Dept. Industrial Engineering, University Trento, Italy
Email: [anonimizat]
Email: [anonimizat]
Abstract —The astonishing evolution in microelectronic sys-
tems pushes the conventional 2D technology to its ultimate limits
in terms of both performance and functionality while reducing
power and cost criteria. To overcome such challenges, using
3D integration with Through Silicon Vias (TSVs) interconnects,
seems to be as a good candidate for the assembly of multilayers
into a single stack. Therefore, in this work, we report on the
evaluation of the impact of TSV interconnects on the electrical
performance of CMOS circuits, particularly the CMOS ring
oscillator, by means of SPICE-like simulations. To this purpose,
an analytical model is used, which is able to describe the behavior
of TSVs and ring oscillator in a circuit level and other phenomena
such as the substrate coupling. This study is made in order to
optimize the performance of a ring oscillator with the presence
of 3D-TSV interconnects as a function of different technological
parameters. The analytical approach has proved its effectiveness
to perform rapid and reliable simulations to investigate the
substrate coupling induced by the TSV on a commonly used
CMOS circuits such as the ring oscillator.
Keywords —3D Integration, 3D-TSV, substrate coupling, CMOS
circuits, ring oscillator.
I. I NTRODUCTION
The microelectronic industry has seen a significant im-
provement over the last few decades on the performance of
Integrated Circuits (ICs) following Moore’s and More than
Moore laws. The latter consists on increasing the density of
transistors on a single chip and incorporating heterogeneous
technologies that do not scale in the same technological node
[1] [2]. To reach these challenges, many novel technologies are
investigated and developed recently including optical intercon-
nects [3], 3-D ICs [4] and silicon interposers [5]. Adopting new
interconnect technologies, as the 3D integration, seems to be
a promising solution to merge both density of integration and
functionally on Integrated Circuits. These three-dimensional
Integrated Circuits can provide as well a reduced power
dissipation and propagation delay and a platform to integrate
different technologies (digital, analog, RF circuits, etc.) on
different active layers [6]. One of the key building blocks from
the numerous aspects of the 3D technology investigated by
many foundries nowadays is the use of a high aspect ratio
vertical interconnects called, Through Silicon Vias (TSVs).
These TSVs feature a deep vertical metal extension throughout
the substrate connecting different layers of ICs into a singlepackage as shown in Fig.1 [7]. This results in an improved
system performance, higher density and a reduced number
of long interconnects as well as their overall length [8] [9].
Due to these benefits, the 3D-TSV technology is gaining a
large interest to the semiconductor industry as a promising
solution to achieve further improvement in circuit performance.
Therefore, a wide range of application of this technology have
been proposed to be exploited in ICs as RF modules, X-ray
detectors, etc [10] [11]. Although this mature technology has
several advantages, the vias may induce electrical coupling and
critical substrate noise in neighboring active devices, which
negatively affects the circuits performance [4] [12] [13]. The
substrate coupling was properly explored in 2D-ICs whether
by measurements or different proposed analytical models [14]
[15]. However, in 3D-IC this noise induced by the TSV on
CMOS circuits has not been adequately studied yet. Therefore,
we present in this paper a comprehensive study to evaluate the
substrate coupling induced by the TSV in a particular circuit
concerning a three-stage ring oscillator. To do so, an electrical
model is considered to evaluate such phenomena using circuit
simulation in which the different components for the model
are defined using an analytic approach. This electrical model
has been validated with TCAD tools in [16] and proved its
effectiveness to perform fast and reliable circuit simulation for
the optimization of the different technological and electrical
parameters that have a direct negative influence on the perfor-
mance of the oscillator. This paper will start first describing the
electrical model and the analytical approach used. Then, we
will focus on the impact of the 3D-interconnects (TSVs) and
the substrate coupling on a three-stage ring oscillator in the
aim of optimizing their performance as a function of several
technological parameters, which is the aim of this paper.
II. S UBSTRATE ELECTRICAL MODEL
The impact of TSVs on the performance of CMOS circuits
can be studied with SPICE-like circuit simulation. To this
purpose, the different components present in the equivalent
circuit are defined using an analytical model. Such an equiv-
alent circuit is composed, on one hand, of MOS transistors,
which are modeled using a BSIM4 compact model, and on the
other hand, of a resistive and capacitive network for the silicon
substrate as well as MOS capacitors for the TSV’s oxide.

Through Silicon ViaCMOS Circuitry
Microchannel3D StackRF CircuitsAnalog CircuitsMemory layerProcessor layerFig. 1. An expanded view that illustrates a 3D IC consisting of multilayer
circuits vertically integrated with TSV interconnects.
A. Substrate network
The silicon substrate has a conductive and dielectric behav-
ior, which can be translated into resistive and capacitive effects,
respectively. The equivalent circuit presenting the coupling
through the substrate, is composed of vertical ( RverandCver)
and lateral ( RLateral andCLateral ) components as shown in
Fig.2. These elements refer to the substrate resistance and
capacitance between the devices contacts and the TSV contact
at some distance, DTSV. These resistances and capacitances
are determined by the following expressions reported in [17]
[18]:
Rver= [K1siSpad
Tsub]1(1)
Cver=K10rSpad
Tsub(2)
RLateral = [K2si
4ln[(DTSVW)
W+t+ 1]W]1(3)
CLateral =K20(r+ 1)
4ln[(DTSVW)
W+t]W (4)
whereTsubis the substrate thickness, Spad= WxW is the
pad surface, siis the silicon conductivity, t is the thickness
of the conductors and DTSV is the distance from the TSV
to the MOS device contacts. K1andK2refer to the fringing
factors, which are illustrated in details in [4] [16], their values
are defined with respect to other circuit geometries (as for the
substrate thickness, Tsuband distance from the TSV to the
devices contacts, DTSV) and used in such a study.
Once taking a look at the physical structure of a studied
circuit, we can assume that it comprises two main areas ac-
cording to their doping concentration. A so-called bulk region
with a constant doping at the bottom and a high doping region,
called the active region, closer to the interface. Therefore,
the bulk region is modeled as an equivalent resistance Rbulk
and capacitance Cbulk while the Active region is modeled as
TSV
Contact
-1-Device
Contact
-1-R
R
Rlat
latverRver
Rver
RverCverCver
Cver CverClat
ClatCoxTSV
CoxTSVRactive
RbulkFig. 2. Lumped equivalent RC model substrate in a silicon substrate.
TSV
Bulk
TSV
Contact
toxR Rmetalox
Noise
couplingDevice
contact
Bulk
Fig. 3. Top view of TSV for capacitor related parameters.
an equivalent resistance Ractive and capacitance Cactive as
shown in Fig.2. The TSV’s contact is placed at the left edge
of the structure and the bulk region is considered with a high
resistivity of a 3.4
.cm while the highly doped region with a
low resistivity of 0.072
.cm [4].
The substrate network elements are determined from the
analytical expressions stated before. Their values are obtained
as a function of different technological parameters (substrate
thicknessTsuband the distance from the TSV to devices’s
contactsDTSV). Vertical or lateral capacitances calculated
from these equations seems to be too small and negligible (less
than 0.2fF). However, the substrate resistances are found to
be so dependent to the structure geometry. This dependence is
shown through Fig.4 & Fig.5 presenting the lateral and vertical
resistance components for both active and bulk regions, this is
as a function of TsubandDTSV, respectively. The vertical
bulk resistance is the one component that is much affected by
the increase of the substrate thickness (the TSV’s length) in
comparison with other resistance elements, which stay almost
constant. On the other hand, the lateral resistances of both
bulk and active regions are the ones that are proportional to
the increase of the distance between the TSV’s contact and
the device’s contact. The lateral resistance of the so-called
active region is higher in such a case due to its low resistivity.

4681012141618200102030405060708090100
Substrate thickness, Tsub [µm]Substrate resistances [k.ohm]

Bulk resistance, Rbulkver
Bulk resistance, Rbulklat
Active resistance, Ractlat
Active resistance, RactverFig. 4. The equivalent vertical and lateral substrate resistances as a function
of the substrate thickness.
234567891005101520253035
Distance from TSV, DTSV [µm] Lateral resistances, [k.ohm]

Bulk resistance, RbulkLat
Active resistance, RactLat
Fig. 5. The equivalent lateral active and bulk resistances as a function of the
distance from TSV contact to device contact.
Therefore, this region is considered as the most sensitive area
and a spot for the substrate coupling that is recommended to
be minimized as much as possible.
B. TSV model
As stated before, the TSV is modelled as a perfect con-
ductor with a considered set of MOS capacitors related to the
TSV oxide layer. The analytical equation of this capacitor is
given as follows [19]:
Cox=2oxTsub
ln(Rox
Rmetal)(5)
whereoxis the oxide permittivity, Roxis the radius
of the oxide of the TSV , Rmetal the radius of the TSV’s
metal andTsubthe substrate thickness (Vias’s length), see
P-Well N-Well
nMOS pMOS
P SubstrateGate Gate
Drain Source Drain Source
n++ n++ p++ p++p+ p+STI
OxideSTI
OxideSTI
OxideSTI
OxideSTI
OxideTSV Isolation
TsubDTSVFig. 6. Physical structure of TSV nearby a CMOS circuit.
Fig.3. Capacitances calculated for different oxide thickness,
Toxis proportional to the substrate thickness; their values are
presented in table. I.
To have more insight on the physical structure of the
considered electrical model studied in this work, Fig.6 shows
in details the most relevant paramters and a TSV placed at the
left edge of a CMOS circuit.
TABLE I. T HETSV OXIDE CAPACITANCE AS A FUNCTION OF THE
SUBSTRATE THICKNESS .
Nsub =2e15A=cm3Tox=0.05mTox=0.25mTox=0.5m
Tsub (m) Cox(fF) Cox(fF) Cox(fF)
5 22.19 4.85 2.67
10 44.39 9.707 5.34
15 66.57 14.54 8.02
20 88.79 19.41 10.68
III. I MPACT OF TSV ON A RING OSCILLATOR
In order to study the impact of TSV on a CMOS circuit,
particularly in this work a three-stage ring oscillator, SPICE-
like circuit simulations are performed using HSpice-Synopsys
circuit analysis tool. The choice for this particular circuit
is dictated by the fact that ring oscillators are valuable test
structure for determining the feasibility and success of an
IC process fabrication sequence. The electrical model for
this study is defined, as stated before, using the different
elements already discussed and calculated from the previous
section and a BSIM4 compact model for MOS transistors of
a 65nm technology with a transistor channel length of 50nm
and a gate oxide thickness of 3.2nm as depicted from [20].
The influence of TSVs on the ring oscillator is studied as
a function of different technological parameters, as for the
substrate thickness ( Tsub) and the distance from the TSV to
MOS devices contacts ( DTSV). To see this impact, an ideal
case of a three-stage ring oscillator, without the presence of
a Through Silicon Via or any induced substrate coupling, is
considered as shown in Fig.7. This is for comparison with
the case of the presence of a TSV nearby the oscillator. The
output signal of the ring oscillator is studied with and without
a TSV by applying a square wave voltage on the via of a
3.3V amplitude, 200ps rise/fall time and 200MHz signal as
presented in Fig.8. The biased voltage VDDis set to 3V along
with load capacitors C1=C2=30fF andC3=60fF.

GND GNDnMOS2C2
30fpMOS2Vdd= 3V
GND GNDnMOS1C1
30fpMOS1Vdd= 3V
GND GNDnMOS3C3
60fpMOS3Vdd= 3V
Fig. 7. Schematics of the circuit of an ideal three-stage ring oscillator without
the impact of a TSV .
pMOS3
nMOS3pMOS2
nMOS2pMOS1
nMOS1GND GND GND
GNDVTSVGND GND GND GND GND GNDV = 3VDD V = 3VDD V = 3VDD
Active region
Bulk region
GND GNDC2 C3 C1
Cact
Cblk30fF 60fF 30fF
Ract-lat
Rblk-latRact-ver
Rblk-verRact-ver
Rblk-ver
Fig. 8. Schematics of the circuit for the impact of TSV on the three-stage
ring oscillator.
The output signal of the oscillator with and without the
impact of a TSV is presented in Fig.9.
The induced influence of the TSV parameters on the behav-
ior of the ring oscillator can be seen through the time delay
per gate. The time delay for this three-stage CMOS ring
oscillator can be determined using the following expression:
=T=2n (6)
Where T is the period and n is the number of gates.
A. The substrate thickness
The first parameter studied in this section concerns the
substrate thickness, Tsub(TSV’s length). This later was varied
in the range from 5 m to 20m [4], which is much reasonable
in a technological process aspect. The time delay induced by a
TSV placed at 6 m away from the oscillator is evaluated, this
is with respect to the ideal case without its presence on the
three-stage ring oscillator. Time delay percentage as a function
00.10.20.30.40.50.60.70.80.91
x 10−800.511.522.533.5
Time [s]Voltage [V]

VTSV
w−TSV
wo−TSVFig. 9. The output Signal of a ring oscillator with and without the impact of
a TSV by applying a square voltage on the TSV . VTSV of a 3.3V amplitude
with 200ps rise/fall time and 200MHz signal.
ofTsubconsidering also another technological parameter, as
for the TSV oxide thickness Tox, is shown in Fig.10. Different
values ofToxwere used in this case; a small oxide thick of
0.05m, which is not recommended to be more reduced in
order not to create isolation issues, and a medium value of
oxide thick of 0.25 m that is better not to be larger to avoid
increasing the TSV diameter.
It could be noted that the substrate thickness has much
effect on the electrical performance of the oscillator increasing
the time delay seen on the output signal. This behavior is
explained simply by the increase of the vertical resistance of
the bulk region allowing the induced TSV’s noise to go mainly
through the low resistance active region. On the other hand,
it was seen that the TSV oxide thick has also a significant
influence on the oscillator performance, increasing its value
reduces the coupling in the substrate, which in turn decreases
the time delay of the oscillator.
B. The distance from the TSV
The other parameter investigated concerns the distance
between the TSV and the CMOS ring oscillator, DTSV. This
later one is varied in a range of values from 2 m up to
10m [4]. The choice for this range was dictated by the fact
that smaller values might cause some misalignment issues and
larger ones wouldn’t maintain the high integration density. The
substrate thickness of silicon substrate is fixed in this case
to 10m and the impact of DTSV, translated by the time
delay induced by the TSV on the ring oscillator, is shown in
Fig.11 using different TSV oxide thicknesses. This time delay
is determined, as previously done, from the comparison of the
output signal with and without the presence of the TSV .
It is clearly seen from the graph that the time delay
percentage has a strong dependence to the distance DTSV, in
other terms, by getting the TSV closer to the ring oscillator this
might increase such a time delay where the substrate coupling
should be higher affecting the performance of the oscillator.

46810121416182005101520
Substrate thickness, Tsub [µm]Time dedelay, [%]

Tox = 0.05µm
Tox = 0.25µmFig. 10. The time delay percentage as a function of the substrate thickness
for different oxide thickness.
234567891011.522.533.544.555.5
Distance from TSV, DTSV [µm]Time delay, [%]

Tox = 0.05µm
Tox = 0.25µm
Fig. 11. The time delay percentage as a function of the distance from the
TSV contact for different oxide thickness.
Moreover, the same concept is also applied for the considered
values ofTox. Such a parameter behaves as a shielding layer
to the noise induced by the via, in which the thicker the oxide
used for the TSV isolation the lower capacitance along the
substrate and the lower influence on the ring oscillator nearby.
IV. C ONCLUSION
The main objective of this work was the evaluation of the
impact of TSVs interconnects on the electrical performance of
a three-stage ring oscillator. An analytical model was imple-
mented and defined proving its effectiveness to describe the
TSVs behavior at the circuit level and other phenomena as the
substrate coupling. The influence of the presence of the TSV
is investigated by means of SPICE-like simulations, showing
promising results to evaluate and optimize the performance
of CMOS circuits with 3D-TSV interconnects as a functionof different technological parameters, thus yielding a useful
design tool.
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