A Novel Standalone Sine Wave Inverter With Reduced Switching Loss [607825]

A NOVEL STANDALONE SINE WAVE
INVERTER WITH REDUCED SWITCHING LOSS
Nanda Kishor Panda , H.Bharadwaj
School of Electrical Engineering
VIT University
Vellore – 632014, India
Email: [anonimizat] ,
[anonimizat] Ramprasad Panda
Department of Electrical Engineering
Silicon Institute of Technology
Bhubaneswar – 75102 4, India
Email: [anonimizat]

Abstract—Sine Pulse Width Modulation (Sine
PWM) is one technology used mostly in power
inverters nowadays to reduce bulky filter
requirements and give a pure sinusoidal wave . This
paper presents a novel standalone sine -wave inverter
utilizing Sine PWM technology in a full bridge
inverter with a modified topology having two
addition al buck switches connected at the output of a
conventional H -Bridge topology. The proposed
inverter uses six switches out of which the 2
additional switches are the only ones operates at high
frequency while the other switches operate at the low
(line) fre quency. This improves the voltage control
and improves the overall efficiency by reducing
switching loss. The above topology aims to reduce the
switching losses by half as compared to a standard H –
Bridge hence increasing the efficiency as well as
increasin g the reliability of the high switching
switches as the operate alternatively for only half
cycle. The proposed topology with switching
technique was simulated and a prototype model was
developed in the laboratory to prove its feasibility.
Index Terms—Sine PWM, H -Bridge, Buck switch,
reliability, efficiency, switching loss.
INTRODUCTION
An inverter is required to transfer power from a
DC source to an AC load and has a wide variety of
applications such as adjustable -speed AC motor
drives, uninterruptible po wer supplies, power
controlling devices, flexible AC transmission
system. A full bride inverter topology consists of
four switching devices as shown. They are
controlled by either PWM techniques or by phase
shifted square wave drives. PWM techniques invol ve the use of high
frequency switches such as MOSFETs which are
operated at far higher frequencies than the output,
thus making the switching harmonic easy to filter.
On the other hand square wave inverters are driven
by the power frequency itself thus lea ding to lower
switching losses while leading to greater harmonic
injection which in turn warrants the need for bulky
filters and additional losses.
There are many PWM techniques such as
unipolar, bipolar, single, multi, modified sine and
phase displacement control [1]. Unipolar switching
tends to be more complex in it s implementation but
results in a better quality of waveform than bipolar
switching. The other techniques [2] tend to provide
better voltage regulation at the cost of w aveform
quality. These PWM techniques are applie d to
generate various waveforms such as sinusoidal,
trapezoidal, staircase, and stepped for modulation.
Of these the Sine PWM is the most commonly used
even though it suffers a drawback of low
fundamental vol tage.
Since most PWM techniques also incur high
switching losses, soft switching techniques are
adopted to reduce them . [3][4]These methods
increase voltage and current stresses on the main
switches by using auxiliary switches and diodes
with higher rating than the main switches, thus
reducing the power output limits.
One of the most efficient PWM te chniques is
Hybrid switching [5][6] where two out of four
switches are driven at high frequency PWM signals
while the others are driven at line frequency square
wave signals. This technique allows the replacement

of the switches driven at lower frequency to be
replaced by devices with much lower switching
speed, which usually have lower conduction losses.
Although total switching losses are reduced in
Hybrid PWM technique, the switching losses are
unequal in all sw itches, especially at higher loads
and higher switching frequencies. Due to this the
reliability of the system reduces as the switches
operating at higher frequencies dissipate more heat
in comparison with the other switches.
In [7] a random switchi ng method for HPWM full
bridge inverter is proposed in which the author
proposed a novel switching technique for HPWM
converters which equalises the switching loss of all
switches.
In this paper instead of giving Sine PWM signals
to the inverter switches, two additional switches are
connected to which the Sine PWM gate signals are
given, each for half the time period. The inverter
switches are operated at line frequency. As only two
switches are operated at high frequency while the
other switches are ope rated at low frequency, overall
switching losses are reduced considerably thus
improving efficiency. This setup allows simpler
control of modulation index and frequency index.
FULL BRIDGE INVERTER
Inverters are classified on the basis of their
operation as voltage sources and current source
inverters. Inverters can also be classified on the basis
of the network as bridge, series and parallel
inverters. Bridge inverters require the use of
switches which are connected in a network and
operated using a contr ol signal in a particular
sequence to obtain the required output waveform.
There exist various kinds of bridge inverters
topologies, foremost of them being have wave and full wave inverters. While half wave inverters utilize
just two switches instead of th e four switches
commonly resent in full wave inverters, they lag
behind in efficiency and waveform quality. A full
bridge inverter topology consists of four switching
devices as shown i n figure (1). They are controlled
by either PWM techniques or by phase shifted
square wave drives.
Full bridge inverters commonly employ PWM
switching techniques to obtain pure sine wave
outputs. This is due to their various advantages
namely,
 Easier control of output voltage
 Minimization of lower order harmonics
 Lower filte r requirements
 Lower power consumption

PWM inverters are classifie d on the basis of their
levels i.e . 2-level and 3 -level as shown in figure (2) .
The simplest way of producing a PWM signal is
through comparison of a low power reference sine
wave with a t riangular wave. Using these two
signals as input to a comparator, the output will be a
Figure 1: Full Bridge Inverter
Figure 2: PWM Levels

2-level PWM signal. In order to create a signal
which is clo ser to a true sine wave, a 3 -level PWM
signal can be generated with high, low and zero
voltage levels. For th e resulting 3 -level PWM signal
to correspond to a sine wave, the signal comparison
state must also be 3 -level. A triangular wave is used
after halving its amplitude ad summing it with a sine
reference signal at a time. The resulting PWM signal
is used to c ontrol one half of the bridge network ,
while the other half of the bridge network, while the
other half controls the polarity of the voltage across
the load and is controlled by a simple square wave
of the same frequency and phase as the sine signal.
Similarly higher levels of PWM can be achi eved
using the previous levels for improved performance.
PROPOSED TOPOLOGY

The proposed topology adds two buck switches
(MOSFET) in back to back connection across the
output of the H -Bridge inverter. The two swi tches
work consecutively in the two positive and negative
half cycles. As shown in figure (3) and (4) they are
connected in series with two diodes to block the
residue currents in closed conditions. In the first
cycle the switch M5 superimposes the positiv e wave
form with Sine PWM whereas the switch M6 does
that in the negative half cycle .
SIMULATION RESULTS
The proposed topology was simulated using
PSIM. The carrier signals generated were (i)
Sinusoidal (50Hz, 8V) and (ii) Unipolar Triangular
(10 kHz, 1 0V). The modulation index was fixed at
0.8(mi=0.8).The circuit was simulated and output
waveform of all the gate signals along with the
waveform of voltage across the load with and
without filers which wer e generated are shown in
figure (5) .

CALCULATION AND DISCUSSION
To check the feasibility of the proposed inverter a
prototype was made in the laboratory. The inverter
was given 50V DC input and operated at 80watts.
The gate signals for S1, S4 and S2, S3 were
generated by using IC LM741 whereas the gate
signal for S5 and S6 were generated from the same
Figure 3: Generation of Sine PWM
Figure 4: Proposed Topology Figure 5: Gate signal and Inverter output without
filter
Figure 6: Inverter output with filter

synchronized carrier signals using IC LM311. All
the gate signals were properly conditioned and
isolated using MOS driver (IR2110) before feeding
it to the gate of the MOSFETs. The MOSFETs used
were IRF540 . The modulation index fo r the Sine
PWM was fixed at 0.8 . The final output was filtered
using a low pass LC filter with corner frequency 1
kHz and 3db disturbances. The various waveforms
at different point were recorded.
Table 1: Switching loss
Parameters Value
tr 44ns
tf 43ns
UDD 300V
IDoff 1A
fsw1 50hz
fsw2 1khz
Switching loss for
circuit shown in fig.1 0.0522W
Switching loss for
proposed topology 0.02871W
The losses [8] incurred in the proposed topology
were compar ed with a standard full bridge inverter
as shown in table 1. The characteristics are
considered for IR2110 MOSFET [9] operating at
25°C and tested with the hardware setup shown in
fig. 9.
Switching loss = (0.5)*U DD*IDoff*(tr+tf)*f sw ..(1)
UDD=Input Voltage
IDoff=Output Current
tr=Rise Time
tf=Fall Time
fsw=Switching Frquency

Figure 7: Gate Signals

Figure 8: Output of Inverter with filter
We can see a saving of 45% in switching losses
between the proposed topology and a standard full
bridge inverter with minimum THD as verified by
the hardware. This showcases the effectiveness of
the proposed topology as a viable alternative and
the cause for f urther development in this design .

Figure 9: Hardware Setup

CONCLUSION
In this paper a full bridge sine wave inverter
using PWM techniques has been proposed with a
change in the standard H -Bridge topology for
improving efficiency. The output of the inverter was
found to be sinusoidal with minimum THD. The
control circuit implemented for the switching is
simple. As only two switches are commutated at
high frequency, the overall switching losses a re
reduced, which make the efficiency high. The
proposed single phase inverter can be used for both
small and medium power applications in the field of
Photovoltaic , backup power in UPS etc. As only two
switches use controllable Sine PWM signals for
harmon ic compensation in active filters, using this
topology will be a viable option for a single phase
system.
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