VHDL CPLD Course [616949]

VHDL CPLD Course
Introduction
This VHDL course introduces the VHDL language and then provides a series
of tutorials that demonstrate the use of VHDL running on a Xilinx CPLD. It
starts with some very basic and easy examples that will get the beginner in
VHDL started comfortably.
The CPLD board used in the tutorials can be built at home. The program-
mer used to congure the CPLD can also be built at home. Both of these
projects are available on this website and can be built on single sided circuit
boards.
The software used to write the VHDL code and program the CPLD is the free
Xilinx ISE software (called WebPACK). In the tutorials it is run on Windows
7.
It is possible to use a dierent CPLD or even FPGA board than the home
made board, in this case the examples will need to be modied to run on the
alternate board. Other CPLD programmers can also be used.
The course uses the following hardware and software. All of these articles
are available on this website and will get you set up with the correct hardware
and software:
Xilinx CPLD Board Electronic Project
Xilinx Parallel Programmer Project ( requires PC with a parallel port )
Installing Xilinx ISE WebPACK 14
Starting a New Xilinx CPLD Project in ISE
VHDL Course Prerequisites
Knowledge Prerequisites
It is assumed that you have some knowledge of logic systems / digital electronics
(e.g. you know what an AND gate is and what an OR gate is, what a truth table
is, etc.) and have built some circuits using IC logic gates. If you do not have
any knowledge of logic systems, there are plenty of books to get you started.
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Hardware and Software Prerequisites
It is assumed that you have built the CPLD board and programmer described
above or that you have obtained a similar board and programmer. It is also
assumed that you have installed the Xilinx WebPACK software and have built
your rst project as described in the relevant articles on this website.

Introduction to VHDL and
CPLD Devices
Here we rst look at what a CPLD is and then look at one of the languages
(VHDL) that can be used to create the logic circuit used to congure a CPLD.
What is a CPLD?
Complex Programmable Logic Devices (CPLDs) are ICs that can be used to
replace circuits built from several logic ICs (e.g. the 74 series of logic devices ?
7400, etc.).
Unlike a discrete logic IC circuit, the logic in the CPLD can be changed
again and again with no need to modify the PCB when changes are made.
One of several Hardware Description Languages (HDL) can be used to create
the logic circuit on a PC. A program is used to convert this logic design into a
format that can be loaded to the CPLD.
The tools used to program a CPLD are very similar to those used to program
an In-System Programmable (ISP) microcontroller. The logic circuit is written
in a text editor or IDE using a hardware description language. The text le
program is then converted to a format that can be loaded into the CPLD. A
JTAG programmer is used to load the logic circuit into the CPLD (congure
the CPLD) while it is soldered in the circuit.
A CPLD has the following features:
Non-volatile memory ? the logic design that is loaded to the CPLD will
not be lost if power to the CPLD is switched o. The logic circuit in the
CPLD will be ready when power to the CPLD is switched on.
Internally a CPLD consists of programmable AND / OR array as well as
macrocells. CPLDs are available in dierent sizes ? both physical (number
of pins / IC package size) and logical (number of gates and macrocells).
What is VHDL?
VHDL is a hardware description language (HDL) that can be used to describe
a logic design. Software tools can then be used to read the VHDL logic design
and produce a conguration le that can be loaded to a CPLD or FPGA which
will then implement the logic design on the CPLD or FPGA.
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Figure 1: Xilinx CPLDs ? PLCC package CPLD and socket (left), VQFP
package CPLD (right)
VHDL stands for VHSIC Hardware Description Language. This is known as
an embedded acronym (an acronym (VHSIC) inside another acronym (VHDL)).
VHSIC stands for Very High Speed Integrated Circuit.
VHDL is standardised by the Institute of Electrical and Electronics Engi-
neers (IEEE) and is a vendor independent language. This makes it portable
and reusable.
Most statements in VHDL occur concurrently (in parallel with each other),
rather than sequentially as normal computer programs do.
One of the alternatives to VHDL is Verilog (also a standardised and vendor
independent HDL).
As this is a practical course, you will learn more about VHDL as you follow
the tutorials. You can read more about VHDL on the Wikipedia VHDL page,
also read about VHSIC on Wikipedia. There are also many books available on
VHDL.

Tutorial 1: VHDL Inverter
and Buer Code
This rst tutorial in the VHDL course shows how to create an inverter in VHDL
code that will invert the signal on a CPLD pin and connect the inverted signal
to an output pin. It also shows how to create a buer in VHDL that simply
connects a signal on an input pin to an output pin of the CPLD.
Examples of how to create inverters and buers on a single input and output
pin as well as an input and output bus are used.
Various elements of the VHDL language are explained during the tutorial as
they are used. You will learn the following in this tutorial:
What the basic elements of a VHDL project consist of
What library les are in VHDL
VHDL entity, architecture and le naming
Dening input and output ports
How to create an inverter and buer
How to create and access a bus in VHDL
Making an Inverter in VHDL
An inverter is a logic gate that converts a logic level on its input to the opposite
logic level on its output, i.e. a 0 on the input of an inverter will produce a 1 on
its output; a 1 on the input of an inverter will produce a 0 in its output.
In this project, the push button on the Xilinx CPLD board is connected to
the input of an inverter implemented in the CPLD that is written in VHDL
code. The output of the inverter is connected to one of the LEDs on the CPLD
board.
This video shows all of the VHDL code for this tutorial and what it does
when run on the home made Xilinx CPLD board:
Can't see the video? View on YouTube
Below is a listing of the VHDL code for the invert VHDL project and an
explanation of various elements in the code. This is followed by information on
how to create the project using the Xilinx tools.
The VHDL code for creating an inverter is as follows, this is the code from
theinvert top.vhd le:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invert_top is
Port ( PB : in STD_LOGIC;
LED : out STD_LOGIC);
end invert_top;
architecture Behavioral of invert_top is
begin
– invert the signal from the push button switch and route it
to the LED ,!
LED <= not PB;
end Behavioral;
VHDL Elements
Library Files
invert top.vhd contains the following statements at the top of the le:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
This includes the IEEE library in the VHDL design and species that all of
theSTD_LOGIC_1164 library package from the IEEE library will be used. You
won't need to know much about libraries at this stage.
VHDL File and Entity Name
The entity describes the pins (or ports) used in the design:
entity invert_top is
Port ( PB : in STD_LOGIC;
LED : out STD_LOGIC);
end invert_top;
The above statements dene an input pin called PB (our push-button switch)
and an output pin called LED (this will connect to one of the LEDs on the
board).
Theentity name in the VHDL le ( invert top.vhd in our example) has
the same name as the VHDL le. In this example the entity name and le name
are both invert_top .
The name invert_top was chosen for this project but could be named any-
thing else. When a new VHDL le is added to the project in the Xilinx software,
it will automatically create the entity code in the le and name it after the cho-
sen le name.
VHDL les end with a .vhd le extension.

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VHDL Architecture
The architecture describes the circuit functionality. This is where the actual
logic design is written in VHDL:
architecture Behavioral of invert_top is
begin
– invert the signal from the push button switch and route it to the LED
LED <= not PB;
end Behavioral;
VHDL Comments
VHDL comments are started with two minus signs next to each other: {
Comments in the VHDL le are ignored by the software tools and allow the
writer of the VHDL to include human readable comments and explanations in
the VHDL le.
Semicolons and Case
Every VHDL statement must be terminated by a semicolon: ;
VHDL is not case sensitive so keywords and statements can be written in
upper or lower case letters.
An Explanation of the VHDL Code
The actual VHDL code that describes the inverter is the single VHDL statement
in the architecture part of the VHDL le:
LED <= not PB;
This statement basically says "Invert the PB input pin and put the inverted
result on the LED pin". The schematic equivalent of this statement is shown in
Figure ??.
The above code inverts the logic level on the PB pin by using the VHDL
notkeyword. It then assigns the inverted logic level to the LED pin using the
VHDL assignment operator <=which places the inverted value on the LED pin.
At this stage, the actual CPLD pin numbers used for PB and LED have not
been dened. This VHDL code is now fully portable and can be moved to a
dierent CPLD or FPGA. The actual pin numbers will be assigned to the pin
names later.
Creating the Project using the Xilinx Software
Create the project by following the steps in the Starting a New Xilinx CPLD
Project in ISE article, but make the following changes:
1. Name the project invert.
2. When the new source le (VHDL module) is added, name it invert top.

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Figure 2: Schematic of the VHDL Inverter Code
3. Specify the ports as PB-an input andLED -an output . Don't check
the Bus checkbox during this step. This step can also be skipped and the
ports dened manually in the VHDL le.
4. Add the line of VHDL code to describe an inverter as already presented
in the code listing above.
5. Create a user constraints le and add the constraints described below.
Adding User Constraints
For the home made CPLD board, add constraints to assign PBto CPLD pin
P3andLED to CPLD pin P26 as shown in the Figure 3. This eectively
connects the input of the inverter to pin 3 of the CPLD (the push button switch
on the CPLD board) and the output of the converter to CPLD pin 26 (one of
the 8 LEDs on the board). You could also assign one of the switches from the
switch bank to the inverter input and any one of the other LEDs to the output
of the inverter.
If you are using a dierent board, then you will need to check which input pin
of the CPLD has a switch connected to it and which one has an LED connected
to it and then assign the correct pins in the UCF le using Xilinx Pace.
Conguring the CPLD
Finish the project by generating the conguration le and then loading the
conguration le to the CPLD.
Source Code
The VHDL le, UCF le and output JED le: invert-src-vhdl-ucf-jed.zip (5.8kB)
The entire Xilinx ISE 14 invert project: invert.zip (684.1kB)

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Figure 3: CPLD Pin Assignment for the Inverter Tutorial – From the Xilinx
Pace Software

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Making a Buer in VHDL
To make a buer, which is the same as connecting and input pin to an output
pin inside the CPLD, change the line of VHDL code to:
LED <= PB;
This just uses the VHDL signal assignment operator to connect the PB input
to the LED output without inverting the input signal.
Inverting or Buering a Bus in VHDL
The Starting a New Xilinx CPLD Project in ISE article uses VHDL code that
implements an 8 bit bus that connects 8 switches to 8 LEDs.
The bus port pins are dened in the entity part of the VHDL code as follows:
Port ( SW : in STD_LOGIC_VECTOR (7 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0));
This code uses the STD_LOGIC_VECTOR type to dene the buses and then
species the size of the bus as 8 bits (7 down to 0) .
The VHDL code for connecting the SW input bus to the LED output bus is
shown below and connects all 8 bits of the buses in a single statement:
LED <= SW;
To invert each signal on the bus, in other words insert an inverter between
each input and output on the bus, use the following VHDL statement:
LED <= not SW;
Don't forget to assign pin numbers in the user constraints le to all of the
pins used in the bus.
Referencing Individual Signals on a Bus in VHDL
When port pins have been dened as being part of a bus, they can be individually
used in the VHDL code as follows:
LED(3) <= SW(5);
This line of code connects the bus line connected to switch 5 of the switch bank
to LED 3 of the set of 8 LEDs on the CPLD board (provided that they are
dened that way in the UCF le).

Tutorial 2: AND Gates, OR
Gates and Signals in VHDL
In this second tutorial of the VHDL course, we look at two basic logic gates,
namely the AND gate and the OR gate. We also look at signals in VHDL.
An interesting problem can occur in a logic design that turns an AND gate
into an OR gate. This same problem also turns an OR gate into an AND gate.
These problems occur because of the external wiring of the logic system when
it inverts inputs and outputs. VHDL signals are used to compensate for this
problem in the CPLD circuit used in this tutorial.
In the VHDL code in this tutorial, you will see the name andorwhich is
the name of the Xilinx project used with this tutorial. A single project was
created to demonstrate both the AND and OR gates. This code is separated
out in the rst listings below to help explain each gate separately.
AND Gates in VHDL
The VHDL for a two input AND gate is shown below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_or_top is
Port ( INA1 : in STD_LOGIC; – AND gate input
INA2 : in STD_LOGIC; – AND gate input
OA : out STD_LOGIC; – AND gate output
end and_or_top;
architecture Behavioral of and_or_top is
begin
OA <= INA1 and INA2; – 2 input AND gate
end Behavioral;
The VHDL andkeyword is used to logically AND the INA1 and INA2 inputs
together. The result of the AND operation is put on the OA output by using
the VHDL <=operator.
This is the equivalent gate described by the above code:
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Figure 4: Schematic Symbol of the AND Gate
OR Gates in VHDL
This is the VHDL code for a two input OR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_or_top is
Port ( INO1 : in STD_LOGIC; – OR gate input
INO2 : in STD_LOGIC; – OR gate input
OO : out STD_LOGIC); – OR gate output
end and_or_top;
architecture Behavioral of and_or_top is
begin
OO <= INO1 or INO2; – 2 input OR gate
end Behavioral;
This code works the same as the AND example, but this time the VHDL or
operator is used to perform a logic OR operation between the two inputs.
This is the equivalent gate described by the above code:
Input and Output Inversion Problem
A problem occurs on the home made Xilinx CPLD board when the above AND
and OR gates are implemented and the switches from the switch bank are used
as inputs to the gates and the LEDs are used as outputs from the gates. This
problem will occur on other boards that have inputs and outputs congured the
same way as the CPLD board.

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Figure 5: Schematic Symbol of the OR Gate
The symptoms of the problem is that the AND gate behaves like an OR
gate; the OR gate behaves like an AND gate.
The reason that this problem is occurring is because of the way the switches
and LEDs are wired on the CPLD board. The switches from the switch bank
change the inputs to the CPLD from high to low when closed. The LEDs switch
on when a low is output from the CPLD to the LEDs.
What this wiring is doing is eectively inverting the inputs to the CPLD and
output from the CPLD: when the switch is closed, we expect to be putting a
logic 1 on the CPLD pin, but we are putting a logic 0 on the CPLD pin instead;
when the output from a CPLD pin is set to a logic 1 level, we are actually
switching the LED o rather than on.
This diagram shows what eectively is happening:
This behaviour of the inverting inputs and outputs can be compensated for
in the VHDL code.
Compensating for the Inverting Switches and LEDs
We can use signals in VHDL to compensate for the inverting switches and
LEDs. Signals can be thought of as being equivalent to variables in computer
programming languages. Signals are internal to the CPLD (or FPGA).
The idea is to create a signal for each input and each output of the gate. The
input values on the gates can now be read from the CPLD pins, then inverted
and assigned to the signals. The outputs of the gates can be assigned to signals
and then inverted before sending the gate output to CPLD output pin. This
compensates for the inverting switches and LEDs by inverting their values so
than an on switch will now read as logic 1; a LED will be switched on by a logic
1.
The VHDL code for both the AND gate and OR gate will now look as

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Figure 6: When Inputs and Outputs of the Gates on the Left are Inverted, they
Eectively Become the Gates Shown on the Right
follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_or_top is
Port ( INA1 : in STD_LOGIC; – input of AND gate
INA2 : in STD_LOGIC; – input of AND gate
OA : out STD_LOGIC; – output of AND gate
INO1 : in STD_LOGIC; – input of OR gate
INO2 : in STD_LOGIC; – input of OR gate
OO : out STD_LOGIC); – output of OR gate
end and_or_top;
architecture Behavioral of and_or_top is
signal A1 : STD_LOGIC; – internal input of AND gate
signal A2 : STD_LOGIC; – internal input of AND gate
signal X1 : STD_LOGIC; – internal output of AND gate
signal B1 : STD_LOGIC; – internal input of OR gate
signal B2 : STD_LOGIC; – internal input of OR gate
signal Y1 : STD_LOGIC; – internal output of OR gate
begin
– old AND gate code commented out
–OA <= INA1 and INA2;
X1 <= A1 and A2; – new AND gate using the inverted internal
signals ,!

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– old OR gate commented out
–OO <= INO1 or INO2;
Y1 <= B1 or B2; – new OR gate using the inverted signals
– compensation for inverting inputs and outputs
A1 <= not INA1; – invert the external input pin and assign
it to AND gate input A1 ,!
A2 <= not INA2; – invert pin INA2, assign to A2 AND gate
input ,!
OA <= not X1; – invert the output of the AND gate, assign
to pin OA ,!
B1 <= not INO1; – etc.
B2 <= not INO2;
OO <= not Y1;
end Behavioral;
In the above code, rst note that signals are declared between the archi-
tecture andbegin statements.
Eectively, the compensation code can now be ignored. The AND gate code
is now this single line:
X1 <= A1 and A2;
The OR gate code is now this:
Y1 <= B1 or B2;
A1, A2, B1 and B2 can be thought of as inputs connected directly to the
switch bank. When a switch is switched on, it can now be thought of as pro-
ducing a logic 1 on the CPLD pin.
X1 and Y1 can be thought of as outputs connecting directly to the LEDs.
To switch an LED on, a logic 1 can be sent to X1 or Y1.
The above assumes that the UCF le has been congured to wire the switches
and LEDs to the gate inputs and outputs.
Concurrency
The above code demonstrates concurrency in VHDL. The statements do not
run sequentially from top to bottom, but rather in parallel. The compensation
code could therefore be put above the gate implementation, or below it.
The AND and OR gates also run in parallel. The code does not rst run the
AND gate part and then the OR gate part.
This video shows the above code running on the home made Xilinx CPLD
board:
Can't see the video? View on YouTube

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Figure 7: Pin Assignment in Xilinx PACE
Creating the Project with the Xilinx Tools
The project can be created using the above code and then using Xilinx PACE
to create the UCF le to connect the inputs of the gates to switches on the
switch bank and outputs to the LEDs.
The pins used on the home made CPLD board for this tutorial are shown
below in Xilinx PACE.
This connects the outer two switches of the switch bank to one gate and the
outer two switches on the opposite side of the switch bank to the other gate.
Source Code
The project created for this tutorial is called andorand the VHDL le is called
andortop.vhd .
VHDL le, UCF le and JED le: and orvhducfjed.zip (5.9kB)
Entire Xilinx project: and or.zip (690.6kB)
Multiple Input AND and OR Gates
A gate with any number of inputs can be created by stringing more inputs
together with AND or OR statements. The following code shows a three input
AND gate:

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X <= A1 and A2 and A3;
Don't forget to add the extra inputs to the Port in the entity part of the
code and then assign a pin on the CPLD using Xilinx PACE.

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Tutorial 3: NAND, NOR,
XOR and XNOR Gates in
VHDL
In the previous tutorial, we looked at AND gates, OR gates and signals in
VHDL. This tutorial covers the remaining gates, namely NAND, NOR, XOR
and XNOR gates in VHDL.
NAND and NOR Logic Gates in VHDL
NAND Gate
The VHDL nand keyword is used to create a NAND gate:
NOR Gate
The VHDL nor keyword is used to create a NOR gate:
NAND and NOR VHDL Project
This code listing shows the NAND and NOR gates implemented in the same
VHDL code. Two separate gates are created that each have two inputs.
Figure 8: NAND gate with truth table and VHDL code
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Figure 9: NOR gate with truth table and VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand_nor_top is
Port ( A1 : in STD_LOGIC; – NAND gate input 1
A2 : in STD_LOGIC; – NAND gate input 2
X1 : out STD_LOGIC; – NAND gate output
B1 : in STD_LOGIC; – NOR gate input 1
B2 : in STD_LOGIC; – NOR gate input 2
Y1 : out STD_LOGIC); – NOR gate output
end nand_nor_top;
architecture Behavioral of nand_nor_top is
begin
X1 <= A1 nand A2; – 2 input NAND gate
Y1 <= B1 nor B2; – 2 input NOR gate
end Behavioral;
The code listing below shows the same code as above, but with compensation
for the inverting inputs on the home made Xilinx CPLD board. The need for
compensation is explained in tutorial 2 AND Gates, OR Gates and Signals in
VHDL.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand_nor_top is
Port ( IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
IN3 : in STD_LOGIC;
IN4 : in STD_LOGIC;
OUT1 : out STD_LOGIC;
OUT2 : out STD_LOGIC);
end nand_nor_top;
architecture Behavioral of nand_nor_top is

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Figure 10: XOR logic gate and truth table with VHDL code
signal A1 : STD_LOGIC;
signal A2 : STD_LOGIC;
signal X1 : STD_LOGIC;
signal B1 : STD_LOGIC;
signal B2 : STD_LOGIC;
signal Y1 : STD_LOGIC;
begin
X1 <= A1 nand A2;
Y1 <= B1 nor B2;
– compensation for inverting inputs and outputs
A1 <= not IN1;
A2 <= not IN2;
OUT1 <= not X1;
B1 <= not IN3;
B2 <= not IN4;
OUT2 <= not Y1;
end Behavioral;
Download nand nor.zip (5.9kB) which contains the VHD, UCF and JED
les for the NAND and NOR gates. The JED le is for conguring the home
made CPLD board.
This video shows the NAND gate and then the NOR gate implemented on
the home made CPLD board.
Can't see the video? View on YouTube
Exclusive-OR and Exclusive-NOR Logic Gates in
VHDL
XOR Gate
The VHDL xorkeyword is used to create an XOR gate:

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Figure 11: XNOR logic gate and truth table with VHDL code
XNOR Gate
The VHDL xnor keyword is used to create an XNOR gate:
XOR and XNOR VHDL Project
This listing shows an XOR and XNOR gate in VHDL.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor_xnor_top is
Port ( A1 : in STD_LOGIC; – XOR gate input 1
A2 : in STD_LOGIC; – XOR gate input 2
X1 : out STD_LOGIC; – XOR gate output
B1 : in STD_LOGIC; – XNOR gate input 1
B2 : in STD_LOGIC; – XNOR gate input 2
Y1 : out STD_LOGIC); – XNOR gate output
end xor_xnor_top;
architecture Behavioral of xor_xnor_top is
begin
X1 <= A1 xor A2; – 2 input exclusive-OR gate
Y1 <= B1 xnor B2; – 2 input exclusive-NOR gate
end Behavioral;
The VHDL code listing below shows the same code as above, but with com-
pensation for inverting inputs and outputs on the board.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor_xnor_top is
Port ( IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
IN3 : in STD_LOGIC;
IN4 : in STD_LOGIC;

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OUT1 : out STD_LOGIC;
OUT2 : out STD_LOGIC);
end xor_xnor_top;
architecture Behavioral of xor_xnor_top is
signal A1 : STD_LOGIC;
signal A2 : STD_LOGIC;
signal X1 : STD_LOGIC;
signal B1 : STD_LOGIC;
signal B2 : STD_LOGIC;
signal Y1 : STD_LOGIC;
begin
X1 <= A1 xor A2;
Y1 <= B1 xnor B2;
– compensation for inverting inputs and outputs
A1 <= not IN1;
A2 <= not IN2;
OUT1 <= not X1;
B1 <= not IN3;
B2 <= not IN4;
OUT2 <= not Y1;
end Behavioral;
Download xor xnor.zip (5.9kB) which contains the VHD, UCF and JED les
for the XOR and XNOR gates. The JED le is for conguring the home made
CPLD board.
This video shows the XOR gate and then the XNOR gate on the home made
CPLD board.
Can't see the video? View on YouTube

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Tutorial 4: Multiplexers in
VHDL
A multiplexer allows digital signals from several sources to be routed onto a
single bus or line. A 'select' input to the multiplexer allows the source of the
signal to be chosen.
We look at two multiplexer examples in this tutorial, the rst multiplexes two
4-bit input buses to a single 4-bit output bus, the second example multiplexes
four single input lines to a single output line.
Four-Bit Wide 2 to 1 Multiplexer
The 2 to 1 multiplexer is shown below. A logic 1 on the SEL line will connect
the 4-bit input bus A to the 4-bit output bus X. A logic 0 on the SEL line will
connect input bus B to output bus X.
VHDL Code
The VHDL code for implementing the 4-bit 2 to 1 multiplexer is shown here.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_2to1_top is
Port ( SEL : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
X : out STD_LOGIC_VECTOR (3 downto 0));
end mux_2to1_top;
architecture Behavioral of mux_2to1_top is
begin
X <= A when (SEL =
1
) else B;
end Behavioral;
The VHDL when andelse keywords are used to implement the multiplexer.
Thewhen-else construct is a conditional signal assignment construct that
assigns the signal on the left of when (A in our example) to the output signal
(X in our example) if the condition to the right of when is true (SEL = '1' ?
if SEL is equal to logic 1). If the condition is false, then the signal to the right
25

26
Figure 12: 4-bit 2 to 1 Multiplexer (MUX)
of the else (B) will be assigned to the output signal instead (this will occur if
the signal on SEL is a logic 0).
The result of this signal assignment is that a logic 1 on SEL will connect the
4-bit input bus A to the 4-bit output bus X. A logic 0 on SEL will connect the
4-bit input bus B to the output bus X.
This video shows the the CPLD with the above code operating.
Can't see the video? View on YouTube
Source Code
The source les for the 4-bit 2 to 1 multiplexer can be downloaded here. The
UCF and JED les are congured for use on the home made CPLD board.
The VHD, UCF and JED les: mux 2to1 4bit.zip (6.1kB)
One-Bit Wide 4 to 1 Multiplexer
A four to one multiplexer that multiplexes single (1-bit) signals is shown below.
The two SEL pins determine which of the four inputs will be connected to the
output.
00 on SEL will connect A(0) to X, 01 on SEL will connect A(1) to X, etc.
VHDL Code
The VHDL code that implements the above multiplexer is shown here.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

27
Figure 13: 1-bit 4 to 1 multiplexer (MUX)
entity mux_4to1_top is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0); – select input
A : in STD_LOGIC_VECTOR (3 downto 0); – inputs
X : out STD_LOGIC); – output
end mux_4to1_top;
architecture Behavioral of mux_4to1_top is
begin
with SEL select
X <= A(0) when "00",
A(1) when "01",
A(2) when "10",
A(3) when "11",

0
when others;
end Behavioral;
In this code, the with ,select andwhen VHDL keywords are used.
The line with SEL select sets up SEL as the signal that is evaluated by
thewhen statements that follow. When the logic levels on SEL match one of
the values to the right of one of the when statements, the signal to the left of
thatwhen statement will be assigned to the output signal (X).
The line containing 'others' is required by VHDL to take care of any logic
combination that is not taken care of by the preceding statements. This allows
for any states besides logic 0 and 1 levels, such as high impedance signals – Z.
Note that single signals are assigned logic values by using single quotes, e.g.
'0'. A group of signals (vectors) are assigned values between double quotes, e.g.

28
"01".
This video shows the the CPLD with the above code operating.
Can't see the video? View on YouTube
Alternate VHDL Code Using when-else
This code implements exactly the same multiplexer as the previous VHDL code,
but uses the VHDL when-else construct. This is the same when-else as the
rst example (2 to 1 MUX), but this time multiple when-else constructs are
used.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_4to1_top is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0); – select input
A : in STD_LOGIC_VECTOR (3 downto 0); – inputs
X : out STD_LOGIC); – output
end mux_4to1_top;
architecture Behavioral of mux_4to1_top is
begin
X <= A(0) when (SEL = "00") else
A(1) when (SEL = "01") else
A(2) when (SEL = "10") else
A(3) when (SEL = "11") else A(0);
end Behavioral;
Source Code
The source les for the 1-bit 4 to 1 multiplexer can be downloaded here. The
UCF and JED les are congured for use on the home made CPLD board.
The VHD, UCF and JED les: mux 4to1 1bit.zip (6.1kB)

Tutorial 5: Decoders in
VHDL
A decoder that has two inputs, an enable pin and four outputs is implemented
in a CPLD using VHDL in this part of the VHDL course.
This 2 to 4 decoder will switch on one of the four active low outputs, de-
pending on the binary value of the two inputs and if the enable input is high.
VHDL processes are introduced in this tutorial ? processes allow sequential
execution of VHDL code contained in them.
Two to Four Decoder
The block diagram of the two to four decoder is shown here.
When the EN pin is low, all the X output pins will be high. With the EN pin
high, all the outputs on the X port will be high, except for the output selected
by the A input port as follows:
00 on the A(1) and A(0) inputs will switch X(0) low
01 on the A(1) and A(0) inputs will switch X(1) low
10 on the A(1) and A(0) inputs will switch X(2) low
11 on the A(1) and A(0) inputs will switch X(3) low
VHDL Code
The two to four decoder is implemented with the following VHDL code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decode_2to4_top is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0); – 2-bit input
X : out STD_LOGIC_VECTOR (3 downto 0); – 4-bit output
EN : in STD_LOGIC); – enable input
end decode_2to4_top;
architecture Behavioral of decode_2to4_top is
begin
process (A, EN)
29

30
Figure 14: 2 to 4 decoder logic element
begin
X <= "1111"; – default output value
if (EN =
1
) then – active high enable pin
case A is
when "00" => X(0) <=
0
;
when "01" => X(1) <=
0
;
when "10" => X(2) <=
0
;
when "11" => X(3) <=
0
;
when others => X <= "1111";
end case;
end if;
end process;
end Behavioral;
This code does the same thing as the previous code, but compensates for
the inverting inputs of the home made CPLD board.
The inverting outputs are left as-is because they are active low and an LED
will switch on, when one of the outputs becomes active.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decode_2to4_top is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0); – 2-bit input
X : out STD_LOGIC_VECTOR (3 downto 0); – 4-bit output
EN : in STD_LOGIC); – enable input
end decode_2to4_top;

31
architecture Behavioral of decode_2to4_top is
signal B : STD_LOGIC_VECTOR(1 downto 0);
begin
B <= not A;
process (B, EN)
begin
X <= "1111"; – default output value
if (EN =
1
) then – active high enable pin
case B is
when "00" => X(0) <=
0
;
when "01" => X(1) <=
0
;
when "10" => X(2) <=
0
;
when "11" => X(3) <=
0
;
when others => X <= "1111";
end case;
end if;
end process;
end Behavioral;
This video shows the above VHDL code implemented on the home made
CPLD board.
Can't see the video? View on YouTube
Source code
The source code for the 2 to 4 decoder can be downloaded here. The UCF and
JED les are congured for the home made CPLD board.
VHD, UCF and JED les: tut5-decoders.zip (6.1kB)
VHDL Code Explanation
Processes
The decoder is implemented within a VHDL process . The code in a process
runs sequentially, unlike the normal concurrent behaviour of VHDL.
A process in VHDL starts with the VHDL process keyword followed by
parentheses: (). The parentheses contain a sensitivity list ? the process is
executed every time a signal in the sensitivity list changes.
The code that makes up the process is contained between begin andend
process; as shown below:
process (A, EN)
begin
– code that runs in the process is put here and runs sequentially
end process;

32
VHDL if Statement
The decoder uses the VHDL ifkeyword. An ifstatment is used in the process
that allows one of the outputs of the decoder to be active only if the enable
(EN) signal is high.
Anifstatement is constructed as follows:
if (EN =
1
) then
– code places here will run only if the condition between parentheses is true
end if;
Anifstatement is started with the ifVHDL keyword followed by parenthe-
ses that contain the conditions being evaluated. Only if this condition is true,
the code between the then keyword and the end if; statement is executed.
In the decoder, the value of the X output lines is set to a default value of
"1111" (all high) using this line of code:
X <= "1111";
This is the rst line of code that runs in the process. If EN is 0, then the
code in the ifconstruct will never run and the X outputs will always be high.
If EN becomes high (logic 1), then the code in the ifconstruct will execute.
VHDL case Statement
Thecase statement operates sequentially and can only be used inside a sequen-
tial block of code such as a process.
The case construct starts with the case keyword followed by an identier
(A in our example) and the iskeyword. The case construct is terminated with
end case;
One or more when statements are contained in the case construct.
In the decoder, the logic level of 0 is applied to the selected output (using
X(?) <=
0
; ) when the A input matches one of the binary values in the when
statements.
case A is
when "00" => X(0) <=
0
;
when "01" => X(1) <=
0
;
when "10" => X(2) <=
0
;
when "11" => X(3) <=
0
;
when others => X <= "1111";
end case;
The default when others statement is necessary even if all the possible
binary input combinations have been taken care of by when statements.

Tutorial 6: Clock Divider in
VHDL
In this tutorial a clock divider is written in VHDL code and implemented in a
CPLD. One LED on the CPLD board is connected to the clock source which is
running at about 130Hz, making the LED appear to be switched on. A second
LED is connected to the clock source divided by 32 which results in the LED

ashing on and o at about 4Hz.
This video shows the VHDL clock divider implemented on a CPLD.
Can't see the video? View on YouTube
Up until now the VHDL course has only looked at combination logic that has
not needed a clock source. Connecting a clock source to the CPLD allows many
sequential logic circuits to be implemented on the CPLD in VHDL. Generating
the Clock Source
A CPLD or FPGA board would typically have an oscillator on the board
that runs in the megahertz (MHz) range to provide a clock source to the CPLD
or FPGA.
The home built CPLD board used in this VHDL course gets its clock source
from an AVR microcontroller on the board. This AVR is used to generate a slow
clock that prevents a massive amount of clock dividing from being necessary in
order to see the outputs of VHDL code operating on the board's LEDs ? a
megahertz clock would need a lot of dividing to make
ashing an LED visible,
this would also use up more of the CPLD's resources.
Before proceeding with this tutorial, it is necessary to load the software to
the ATtiny2313 AVR microcontroller on the board so that it can generate the
slow clock needed in the tutorials.
The clock pulse has been generated purely in software. The source code for
the clock generating software can be downloaded below.
AVR clock pulse Atmel Studio project: AVR CLK.zip (14kB)
Load this program to the ATtiny2313 microcontroller on the CPLD board.
More information on loading software to and testing the AVR and CPLD can
be found at the bottom of the CPLD board project page (look under "Final
Testing").
Clock Divider VHDL Code
The VHDL source code for the clock divider is shown below.
33

34
Figure 15: Programming the AVR Microcontroller and the Xilinx CPLD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock_divider_top is
Port ( CLK_PB4 : in STD_LOGIC;
LED1 : out STD_LOGIC;
LED2 : out STD_LOGIC);
end clock_divider_top;
architecture Behavioral of clock_divider_top is
signal CLK_DIV : std_logic_vector (4 downto 0);
begin
– clock divider
process (CLK_PB4)
begin
if (CLK_PB4
Event and CLK_PB4 =
1
) then
CLK_DIV <= CLK_DIV +
1
;
end if;
end process;
LED1 <= CLK_PB4; – connect LED 1 to clock source
LED2 <= CLK_DIV(4); – connect LED 2 to divided clock
end Behavioral;
The above source code can be downloaded here:
VHDL, UCF and JED les for the clock divider tutorial: clock divider vhdl.zip
(5.9kB)

35
Libraries
The rst thing to note about the above code is that an extra library module
has been included:
use IEEE.STD_LOGIC_UNSIGNED.ALL;
This is necessary in order to do the addition later in the code. Try comment-
ing this line of code out and see what error message the development software
gives when running the synthesize step.
Structure
The entity part of the code describes a logic element with a clock source on
input pin CLK_PB4 and two output LEDs. CLK_PB4 is the clock pulse from pin
PB4 of the AVR on the board.
Clock Divider
The clock divider has been implemented in a VHDL process (covered in the
previous tutorial).
The clock source, CLK_PB4 is in the sensitivity list of the process, so the
process will be run every time there is a change on the clock input.
The if statement in the process checks if there has been a change in the logic
level of the clock pulse ( CLK_PB4
Event ) and if the clock pulse is currently high
(CLK_PB4 =
1
) ? in other words it is looking for each rising edge of the clock
pulse.
On every rising edge of the clock pulse, the 5 bit CLK_DIV signal (register)
will be incremented by 1. Bit 0 of CLK_DIV will therefore toggle at half the
clock rate, Bit 1 will toggle at half the rate of bit 0, etc. until we get to bit 4 of
CLK_DIV which eectively divides the clock pulse by 32.
Thus our clock source of 130Hz (approximate frequency of this inaccurate
clock source) will be divided down to approximately 4Hz when sampled from
bit 4 ofCLK_DIV .
Outputs
LED1 <= CLK_PB4; simply routes the source clock (130Hz) to LED 1.
LED2 <= CLK_DIV(4); routes bit 4 of the CLK_DIV register to LED 2. This is input clock pulse divided by 32.
We can now compare the input clock (output on LED 1) with the divided output
clock on LED 2 to see the dierence.
These two clock sources can now be measured using a frequency meter (or
frequency scale on a multimeter) or viewed on an oscilloscope (although the 4Hz
is a bit slow for the scope, so try changing the VHDL to route one of the other
bits ofCLK_DIV to LED 2).

36

Tutorial 7: Binary Counter
in VHDL
This tutorial shows how to create a binary counter in VHDL. The counter is
really only a modication of the clock divider from the previous tutorial.
The value of the eight-bit counter is shown on eight LEDs on the CPLD
board.
This video shows the binary counter in operation.
Can't see the video? View on YouTube
CPLD Board Conguration
It is necessary to have a clock pulse supplied to the CPLD for this tutorial.
This is supplied to pin P7 of the CPLD from the AVR on the home built CPLD
board as described in tutorial 6.
Binary Counter VHDL Code
The VHDL code listing for the binary counter is shown below.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity binary_counter_top is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end binary_counter_top;
architecture Behavioral of binary_counter_top is
signal CLK_DIV : std_logic_vector (2 downto 0);
signal COUNT : std_logic_vector (7 downto 0);
begin
– clock divider
process (CLK)
37

38
begin
if (CLK
Event and CLK =
1
) then
CLK_DIV <= CLK_DIV +
1
;
end if;
end process;
– counter
process (CLK_DIV(2))
begin
if (CLK_DIV(2)
Event and CLK_DIV(2) =
1
) then
COUNT <= COUNT +
1
;
end if;
end process;
– display the count on the LEDs
LED <= not COUNT;
end Behavioral;
Source Code
The VHDL source code with UCF and JED les can be downloaded here:
VHDL-binary-counter.zip (6.2kB). Libraries
Again, note that the STD_LOGIC_UNSIGNED module of the IEEE library is
necessary and is included with the use statement at the top of the le.
Clock Divider
A clock divider, covered in the previous tutorial, has been used to provide a
slower clock to the binary counter. This slow clock makes it possible to see the
binary value counting up on the LEDs.
Binary Counter
The binary counter is contained in a VHDL process with the input clock divided
by 8 (CLK_DIV(2) ) in its sensitivity list. This supplies a clock of about 16.25Hz
when using an input clock of about 130Hz (as supplied by the AVR).
The binary counter works exactly the same way as the clock divider, but
consists of eight bits.
The COUNT register contains the binary counter value and is incremented
on every rising clock edge of the clock divider. The value of the COUNT register
is displayed on the LEDs with the code LED <= not COUNT; which inverts the
count value to compensate for the inverting LED outputs on the home built
CPLD board.
The binary counter could also have been implemented using an 11-bit register
and then connecting the top 8 bits of the register to the LEDs. This would then
run the counter at the same speed as the above counter with clock divider.

Tutorial 8: LED Knight
Rider Display in VHDL
A LED chaser type knight rider display with 8 LEDs written in VHDL and
implemented on a CPLD.
This video shows the knight-rider display on the home built CPLD board.
Can't see the video? View on YouTube
Knight Rider VHDL Code
The code listing for the LED knight rider display is shown below.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity knight_top is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end knight_top;
architecture Behavioral of knight_top is
signal clk_div : std_logic_vector(4 downto 0);
signal shift_reg : std_logic_vector(7 downto 0) := X"01";
signal fwd : std_logic :=
1
;
begin
– clock divider
process (CLK)
begin
if (CLK
Event and CLK =
1
) then
clk_div <= clk_div +
1
;
end if;
end process;
– knight rider display
39

40
process (clk_div(4))
begin
if (clk_div(4)
Event and clk_div(4) =
1
) then
if (fwd =
1
) then
shift_reg <= shift_reg(6 downto 0) &
0
;
if (shift_reg = X"40") then
fwd <=
0
;
end if;
else
shift_reg <=
0
& shift_reg(7 downto 1);
if (shift_reg = X"02") then
fwd <=
1
;
end if;
end if;
end if;
end process;
– display the result on the LEDs
LED <= not shift_reg;
end Behavioral;
Source Code
The above VHDL source code with the UCF and JED les can be downloaded
here: knight-rider-VHDL.zip (6.3kB)
Clock Divider
A clock divider is is used to slow down the input clock and make the knight
rider display slow enough to see. The input clock is a 130Hz clock from the
AVR on the board (see tutorial 6 for information on how to set the clock up).
Initializing Registers
In the line of code signal shift_reg : std_logic_vector(7 downto 0) := X"01";
the 8-bit register shift_reg is initialized to a hexadecimal value of 01. The 1
represents the LED that will be on in the display.
The value is assigned to the register using the VHDL :=operator and is
declared to be a hexadecimal number by preceding the number with X.
The fwd signal is also assigned a default value which is a single bit value of
1.
Knight Rider Process
The knight rider process is driven by the rising edge of the divided clock pulse.
The shift register shift_reg contains 0x01 initially and the fwd signal indicates
that the display is moving in the forward direction (i.e. shifting from right to
left).

41
On each clock pulse, the value in shift_reg is shifted left once until the
upper bit in shift_reg contains the high bit (logic 1 bit). The fwd signal
ag
will then be changed to a value of 0, indicating that the direction of shifting
will be reversed (i.e. start shifting from left to right).
The fwd
ag is checked in the VHDL if-then-else-endif construct. If fwd
contains 1, the code under the if statement will run. If fwd contains 0, the code
under the else statement will run.
When fwd is cleared, shifting takes place from left to right until the high bit
has been moved to the rst bit position in shift_reg . fwd will then be set to
1 and the whole process starts again. LED Outputs
The code LED <= not shift_reg; displays the value of the shift register on
the LEDs. It inverts the value in the shift register using the VHDL not keyword
to compensate for the inverting LEDs on the home built CPLD board.

42

Tutorial 9: S-R Latch in
VHDL
In this tutorial, a S-R latch is designed and written in VHDL, it is then imple-
mented on a Xilinx CPLD.
This video shows the VHDL S-R latch operating.
Can't see the video? View on YouTube
S-R Latch Operation
An S-R latch (set-reset latch) made from two NOR gates is shown below. This
latch has active high inputs.
The S-R latch is implemented as shown below in this VHDL example. The
not Q output is left internal to the latch and is not taken to an external pin.
The not Q pin will always be at the opposite logic level as the Q pin.
How the S-R Latch Works
S and R Inputs Both Low
With both the S and R inputs at logic 0 level, the Q output will be latched at
whatever value it was at. When at logic 0, the S and R inputs do not in
uence
the output of the latch.
R Input Goes High and Low
When R goes high, the latch is reset ? meaning that Q goes low. This assumes
that S is low. If R goes low again, the output of the latch will remain latched
low.
In other words, a positive pulse on R resets Q when S is low.
S Input Goes High and Low
With R low, when the S input goes high, the output of the latch will go high.
If S is taken low after this, the Q output will remain latched high.
In other words, a positive pulse on S sets Q when R is low.
43

44
Figure 16: S-R latch made from NOR gates, active high inputs
Figure 17: S-R latch and symbol as implemented in VHDL

45
R and S Both High
R and S must never be allowed to go high at the same time. This is an undened
state for this type of latch.
S-R Latch Design in VHDL
Before reading further, take a few minutes to think how you would design this
latch using the VHDL that you have learned so far on this course.
Inputs and Outputs
The rst thing to do would be to dene the input and output pins:
entity S_R_latch_top is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : out STD_LOGIC);
end S_R_latch_top;
S-R Latch Logic
Next, the logic needs to be designed using VHDL code. The not Q output will
need to be dened as an internal signal as it is still part of the S-R latch, even
though it was decided not to wire it to the outside of the latch. This signal will
be added to the architecture part of the code.
architecture Behavioral of S_R_latch_top is
signal notQ : STD_LOGIC;
begin
– the VHDL logic design of the S-R latch will go here
end Behavioral;
Let's take another look at the S-R latch and then design the logic.
The Q output is made by NORing its two inputs. Its two inputs are R and
the output of the second NOR gate ? not Q. The VHDL code for the top NOR
gate would then look like this.
Q <= R nor notQ;
The not Q output is made by NORing S and Q together. This is now added to
the VHDL code.
notQ <= S nor Q;
The nal VHDL code will now look like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity S_R_latch_top is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;

46
Figure 18: S-R latch made from NOR gates, active high inputs
Q : out STD_LOGIC);
end S_R_latch_top;
architecture Behavioral of S_R_latch_top is
signal notQ : STD_LOGIC;
begin
Q <= R nor notQ;
notQ <= S nor Q;
end Behavioral;
Synthesizing the VHDL S-R Latch
When the above code is synthesized, e.g. by using the Xilinx software tools, an
error will be generated.
The error from the Xilinx tools states: Parameter Q of mode out can
not be associated with a formal parameter of mode in .
This error is occurring because Q is an output and its value can't be read ?
i.e. it is read when NORing S and Q together to generate the notQ output.
Solving the Problem ? Method 1
One way of solving this problem is to use another internal signal that will contain
the value of Q. We will then be able to read this signal.

47
architecture Behavioral of S_R_latch_top is
signal notQ : STD_LOGIC;
signal Q2 : STD_LOGIC; – a copy of the Q output
begin
Q <= R nor notQ;
Q2 <= R nor notQ; – a copy of Q
notQ <= S nor Q2; – use the copy of Q
end Behavioral;
The above logic can be further simplied by performing the NOR operation for
the Q output only once:
Q <= Q2;
Q2 <= R nor notQ; – a copy of Q
notQ <= S nor Q2; – use the copy of Q
Remember that the above statements are running concurrently, so it does not
matter which order the statements are in.
The nal VHDL code for this solution will now look like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity S_R_latch_top is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : out STD_LOGIC);
end S_R_latch_top;
architecture Behavioral of S_R_latch_top is
signal Q2 : STD_LOGIC;
signal notQ : STD_LOGIC;
begin
Q <= Q2;
Q2 <= R nor notQ;
notQ <= S nor Q2;
end Behavioral;
Solving the Problem ? Method 2
An even simpler method of solving this problem is to dene the Q pin of type
inout instead of out. This makes the Q pin readable within the VHDL code.
We can now take our original VHDL code and simply change outtoinout :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity S_R_latch_top is

48
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : inout STD_LOGIC); – changed out to inout
end S_R_latch_top;
architecture Behavioral of S_R_latch_top is
signal notQ : STD_LOGIC;
begin
Q <= R nor notQ;
notQ <= S nor Q;
end Behavioral;
Source Code for Solutions
This source code is for the above two solutions to creating a S-R latch in VHDL.
The VHDL, UCF and JED les are included. The UCF and JED les are
congured for the home built CPLD board.
Solution 1: S Rlatch.zip (5.8kB)
Solution 2: S Rlatch inout.zip (5.8kB)